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frame_grabber_hw.tcl @ 136

Last change on this file since 136 was 87, checked in by lambert, 11 years ago
Adding generation simulation support for verilog
File size: 5.6 KB

Line
1	# TCL File Generated by Component Editor 13.1
2	# Mon Mar 03 15:33:08 CET 2014
3	# DO NOT MODIFY
4
5
6	#
7	# frame_grabber "frame_grabber" v1.0
8	# 2014.03.03.15:33:08
9	#
10	#
11
12	#
13	# request TCL package from ACDS 13.1
14	#
15	package require -exact qsys 13.1
16
17
18	#
19	# module frame_grabber
20	#
21	set_module_property DESCRIPTION ""
22	set_module_property NAME frame_grabber
23	set_module_property VERSION 1.0
24	set_module_property INTERNAL false
25	set_module_property OPAQUE_ADDRESS_MAP true
26	set_module_property GROUP smartEEG
27	set_module_property AUTHOR ""
28	set_module_property DISPLAY_NAME frame_grabber
29	set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
30	set_module_property EDITABLE true
31	set_module_property ANALYZE_HDL AUTO
32	set_module_property REPORT_TO_TALKBACK false
33	set_module_property ALLOW_GREYBOX_GENERATION false
34
35
36	#
37	# file sets
38	#
39	add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
40	set_fileset_property QUARTUS_SYNTH TOP_LEVEL frame_grabber
41	set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
42	add_fileset_file frame_grabber.v VERILOG PATH frame_grabber.v TOP_LEVEL_FILE
43
44	add_fileset SIM_VERILOG SIM_VERILOG "" ""
45	set_fileset_property SIM_VERILOG TOP_LEVEL frame_grabber
46	set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
47	add_fileset_file frame_grabber.v VERILOG PATH frame_grabber.v
48
49
50	#
51	# parameters
52	#
53
54
55	#
56	# display items
57	#
58
59
60	#
61	# connection point clock
62	#
63	add_interface clock clock end
64	set_interface_property clock clockRate 0
65	set_interface_property clock ENABLED true
66	set_interface_property clock EXPORT_OF ""
67	set_interface_property clock PORT_NAME_MAP ""
68	set_interface_property clock CMSIS_SVD_VARIABLES ""
69	set_interface_property clock SVD_ADDRESS_GROUP ""
70
71	add_interface_port clock clk clk Input 1
72
73
74	#
75	# connection point reset
76	#
77	add_interface reset reset end
78	set_interface_property reset associatedClock clock
79	set_interface_property reset synchronousEdges DEASSERT
80	set_interface_property reset ENABLED true
81	set_interface_property reset EXPORT_OF ""
82	set_interface_property reset PORT_NAME_MAP ""
83	set_interface_property reset CMSIS_SVD_VARIABLES ""
84	set_interface_property reset SVD_ADDRESS_GROUP ""
85
86	add_interface_port reset reset reset Input 1
87
88
89	#
90	# connection point ctrl
91	#
92	add_interface ctrl avalon end
93	set_interface_property ctrl addressUnits WORDS
94	set_interface_property ctrl associatedClock clock
95	set_interface_property ctrl associatedReset reset
96	set_interface_property ctrl bitsPerSymbol 8
97	set_interface_property ctrl burstOnBurstBoundariesOnly false
98	set_interface_property ctrl burstcountUnits WORDS
99	set_interface_property ctrl explicitAddressSpan 0
100	set_interface_property ctrl holdTime 0
101	set_interface_property ctrl linewrapBursts false
102	set_interface_property ctrl maximumPendingReadTransactions 0
103	set_interface_property ctrl readLatency 0
104	set_interface_property ctrl readWaitTime 1
105	set_interface_property ctrl setupTime 0
106	set_interface_property ctrl timingUnits Cycles
107	set_interface_property ctrl writeWaitTime 0
108	set_interface_property ctrl ENABLED true
109	set_interface_property ctrl EXPORT_OF ""
110	set_interface_property ctrl PORT_NAME_MAP ""
111	set_interface_property ctrl CMSIS_SVD_VARIABLES ""
112	set_interface_property ctrl SVD_ADDRESS_GROUP ""
113
114	add_interface_port ctrl avs_s0_address address Input 8
115	add_interface_port ctrl avs_s0_read read Input 1
116	add_interface_port ctrl avs_s0_readdata readdata Output 32
117	add_interface_port ctrl avs_s0_write write Input 1
118	add_interface_port ctrl avs_s0_writedata writedata Input 32
119	add_interface_port ctrl avs_s0_waitrequest waitrequest Output 1
120	set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
121	set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
122	set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
123	set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
124
125
126	#
127	# connection point raw_video
128	#
129	add_interface raw_video avalon_streaming start
130	set_interface_property raw_video associatedClock clock
131	set_interface_property raw_video associatedReset reset
132	set_interface_property raw_video dataBitsPerSymbol 8
133	set_interface_property raw_video errorDescriptor ""
134	set_interface_property raw_video firstSymbolInHighOrderBits true
135	set_interface_property raw_video maxChannel 0
136	set_interface_property raw_video readyLatency 0
137	set_interface_property raw_video ENABLED true
138	set_interface_property raw_video EXPORT_OF ""
139	set_interface_property raw_video PORT_NAME_MAP ""
140	set_interface_property raw_video CMSIS_SVD_VARIABLES ""
141	set_interface_property raw_video SVD_ADDRESS_GROUP ""
142
143	add_interface_port raw_video aso_out0_data data Output 32
144	add_interface_port raw_video aso_out0_ready ready Input 1
145	add_interface_port raw_video aso_out0_valid valid Output 1
146
147
148	#
149	# connection point conduit_camera
150	#
151	add_interface conduit_camera conduit end
152	set_interface_property conduit_camera associatedClock clock
153	set_interface_property conduit_camera associatedReset ""
154	set_interface_property conduit_camera ENABLED true
155	set_interface_property conduit_camera EXPORT_OF ""
156	set_interface_property conduit_camera PORT_NAME_MAP ""
157	set_interface_property conduit_camera CMSIS_SVD_VARIABLES ""
158	set_interface_property conduit_camera SVD_ADDRESS_GROUP ""
159
160	add_interface_port conduit_camera D5M_D export Input 12
161	add_interface_port conduit_camera D5M_RESETn export Output 1
162	add_interface_port conduit_camera D5M_FVAL export Input 1
163	add_interface_port conduit_camera D5M_LVAL export Input 1
164	add_interface_port conduit_camera D5M_PIXLCLK export Input 1
165	add_interface_port conduit_camera D5M_SCLK export Output 1
166	add_interface_port conduit_camera D5M_SDATA export Bidir 1
167	add_interface_port conduit_camera D5M_STROBE export Input 1
168	add_interface_port conduit_camera D5M_TRIGGER export Output 1
169	add_interface_port conduit_camera D5M_XCLKIN export Output 1
170

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source: PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber/frame_grabber_hw.tcl @ 136

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