source: PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber

Name Size Rev Age Author Last Change
../
signal_grabber.v 2.3 KB ​ 89   11 years szahmed Added Headline comments for Verilog files explaining their brief …
signal_grabber_hw.tcl 7.9 KB ​ 87   11 years lambert Adding generation simulation support for verilog
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