[89] | 1 | /******************************************************************** |
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| 2 | * COPYRIGHT LIP6 2014 |
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| 3 | *-----------------------------------------------------------------*/ |
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| 4 | /** |
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| 5 | * @file signal_grabber.v |
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| 6 | * @brief Performs signal grabbing of EXG and Audio data coming from ETIS |
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| 7 | * |
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| 8 | * This module performs grabbing of time-stamped EXG and Audio data coming from ETIS (In initial versions create dummy/test data via internal logic of |
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| 9 | * this module for validation of rest of the system). It sends the data received/Modeled from/of ETIS to Audio and EXG coders via AvalonST source |
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| 10 | * |
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| 11 | * @author S. Z. Ahmed <syed-zahid.ahmed@lip6.fr> |
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| 12 | * @author L. Lambert <laurent.lambert@lip6.fr> |
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| 13 | * @date Fri. 28 Feb. 2014 |
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| 14 | * |
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| 15 | * Revision History |
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| 16 | * @version V1.0 Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui} |
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| 17 | * |
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| 18 | *******************************************************************/ |
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[83] | 19 | |
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| 20 | `timescale 1 ps / 1 ps |
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| 21 | module signal_grabber #( |
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| 22 | parameter ctrl_addr_width = 32, |
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| 23 | parameter ctrl_data_width = 32, |
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| 24 | parameter audio_str_width = 32, |
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| 25 | parameter exg_str_width = 32, |
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| 26 | parameter etis_si_width = 32 |
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| 27 | ) ( |
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| 28 | input wire clk, // clock.clk |
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| 29 | input wire reset, // reset.reset |
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| 30 | input wire [ctrl_addr_width-1:0] avs_ctrl_address, // ctrl.address |
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| 31 | input wire avs_ctrl_read, // .read |
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| 32 | output wire [31:0] avs_ctrl_readdata, // .readdata |
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| 33 | input wire avs_ctrl_write, // .write |
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| 34 | input wire [31:0] avs_ctrl_writedata, // .writedata |
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| 35 | output wire avs_ctrl_waitrequest, // .waitrequest |
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| 36 | output wire [31:0] aso_raw_audio_data, // audio.data |
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| 37 | input wire aso_raw_audio_ready, // .ready |
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| 38 | output wire aso_raw_audio_valid, // .valid |
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| 39 | output wire [31:0] aso_raw_exg_data, // exg.data |
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| 40 | input wire aso_raw_exg_ready, // .ready |
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| 41 | output wire aso_raw_exg_valid |
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| 42 | ); |
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| 43 | |
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| 44 | // TODO: Auto-generated HDL template |
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| 45 | |
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| 46 | assign avs_ctrl_waitrequest = 1'b0; |
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| 47 | |
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| 48 | assign avs_ctrl_readdata = 32'b00000000000000000000000000000000; |
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| 49 | |
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| 50 | assign aso_raw_audio_valid = 1'b0; |
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| 51 | |
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| 52 | assign aso_raw_audio_data = 32'b00000000000000000000000000000000; |
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| 53 | |
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| 54 | assign aso_raw_exg_valid = 1'b0; |
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| 55 | |
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| 56 | assign aso_raw_exg_data = 32'b00000000000000000000000000000000; |
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| 57 | |
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| 58 | assign asi_etis_ready = 1'b0; |
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| 59 | |
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| 60 | endmodule |
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