source: PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber @ 87

Name Size Rev Age Author Last Change
../
signal_grabber.v 1.8 KB ​ 84   10 years lambert Adding hierarchical subdirectory for every component
signal_grabber_hw.tcl 7.9 KB ​ 87   10 years lambert Adding generation simulation support for verilog
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