Changeset 87 for PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber

Timestamp:

Mar 3, 2014, 4:09:09 PM (11 years ago)

Author:

lambert

Message:

Adding generation simulation support for verilog

File:

• PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber/signal_grabber_hw.tcl (modified) (3 diffs)

PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber/signal_grabber_hw.tcl

@@ -1 +1 @@
 # TCL File Generated by Component Editor 13.1
-# Fri Feb 28 17:57:56 CET 2014
+# Mon Mar 03 15:33:43 CET 2014
 # DO NOT MODIFY
 
@@ -6 +6 @@
 # 
 # signal_grabber "signal_grabber" v1.0
-#  2014.02.28.17:57:56
+#  2014.03.03.15:33:43
 # 
 # 
@@ -41 +41 @@
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 add_fileset_file signal_grabber.v VERILOG PATH signal_grabber.v TOP_LEVEL_FILE
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG TOP_LEVEL signal_grabber
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file signal_grabber.v VERILOG PATH signal_grabber.v