[83] | 1 | // stream_merger.v |
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| 2 | |
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| 3 | // This file was auto-generated as a prototype implementation of a module |
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| 4 | // created in component editor. It ties off all outputs to ground and |
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| 5 | // ignores all inputs. It needs to be edited to make it do something |
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| 6 | // useful. |
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| 7 | // |
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| 8 | // This file will not be automatically regenerated. You should check it in |
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| 9 | // to your version control system if you want to keep it. |
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| 10 | |
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| 11 | `timescale 1 ps / 1 ps |
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| 12 | module stream_merger #( |
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| 13 | parameter AUTO_CLOCK_CLOCK_RATE = "-1" |
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| 14 | ) ( |
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| 15 | input wire clk, // clock.clk |
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| 16 | input wire reset, // reset.reset |
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| 17 | input wire [7:0] avs_ctrl_address, // ctrl.address |
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| 18 | input wire avs_ctrl_read, // .read |
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| 19 | output wire [31:0] avs_ctrl_readdata, // .readdata |
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| 20 | input wire avs_ctrl_write, // .write |
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| 21 | input wire [31:0] avs_ctrl_writedata, // .writedata |
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| 22 | output wire avs_ctrl_waitrequest, // .waitrequest |
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| 23 | input wire [31:0] asi_raw_video_data, // raw_video.data |
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| 24 | output wire asi_raw_video_ready, // .ready |
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| 25 | input wire asi_raw_video_valid, // .valid |
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| 26 | input wire [31:0] asi_raw_exg_data, // raw_exg.data |
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| 27 | output wire asi_raw_exg_ready, // .ready |
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| 28 | input wire asi_raw_exg_valid, // .valid |
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| 29 | input wire [31:0] asi_comp_video_data, // comp_video.data |
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| 30 | output wire asi_comp_video_ready, // .ready |
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| 31 | input wire asi_comp_video_valid, // .valid |
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| 32 | input wire [31:0] asi_comp_exg_data, // comp_exg.data |
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| 33 | output wire asi_comp_exg_ready, // .ready |
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| 34 | input wire asi_comp_exg_valid, // .valid |
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| 35 | input wire [31:0] asi_comp_audio_data, // comp_audio.data |
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| 36 | output wire asi_comp_audio_ready, // .ready |
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| 37 | input wire asi_comp_audio_valid // .valid |
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| 38 | ); |
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| 39 | |
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| 40 | // TODO: Auto-generated HDL template |
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| 41 | |
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| 42 | assign avs_ctrl_waitrequest = 1'b0; |
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| 43 | |
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| 44 | assign avs_ctrl_readdata = 32'b00000000000000000000000000000000; |
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| 45 | |
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| 46 | assign asi_in0_ready = 1'b0; |
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| 47 | |
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| 48 | endmodule |
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