1 | # TCL File Generated by Component Editor 13.1 |
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2 | # Mon Mar 03 15:30:43 CET 2014 |
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3 | # DO NOT MODIFY |
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4 | |
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5 | |
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6 | # |
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7 | # stream_merger "stream_merger" v1.0 |
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8 | # 2014.03.03.15:30:43 |
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9 | # |
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10 | # |
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11 | |
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12 | # |
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13 | # request TCL package from ACDS 13.1 |
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14 | # |
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15 | package require -exact qsys 13.1 |
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16 | |
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17 | |
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18 | # |
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19 | # module stream_merger |
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20 | # |
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21 | set_module_property DESCRIPTION "" |
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22 | set_module_property NAME stream_merger |
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23 | set_module_property VERSION 1.0 |
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24 | set_module_property INTERNAL false |
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25 | set_module_property OPAQUE_ADDRESS_MAP true |
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26 | set_module_property GROUP smartEEG |
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27 | set_module_property AUTHOR "" |
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28 | set_module_property DISPLAY_NAME stream_merger |
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29 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true |
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30 | set_module_property EDITABLE true |
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31 | set_module_property ANALYZE_HDL AUTO |
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32 | set_module_property REPORT_TO_TALKBACK false |
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33 | set_module_property ALLOW_GREYBOX_GENERATION false |
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34 | |
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35 | |
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36 | # |
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37 | # file sets |
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38 | # |
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39 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" |
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40 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL stream_merger |
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41 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false |
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42 | add_fileset_file stream_merger.v VERILOG PATH stream_merger.v TOP_LEVEL_FILE |
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43 | |
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44 | add_fileset SIM_VERILOG SIM_VERILOG "" "" |
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45 | set_fileset_property SIM_VERILOG TOP_LEVEL stream_merger |
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46 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false |
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47 | add_fileset_file stream_merger.v VERILOG PATH stream_merger.v |
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48 | |
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49 | |
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50 | # |
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51 | # parameters |
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52 | # |
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53 | |
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54 | |
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55 | # |
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56 | # display items |
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57 | # |
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58 | |
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59 | |
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60 | # |
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61 | # connection point clock |
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62 | # |
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63 | add_interface clock clock end |
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64 | set_interface_property clock clockRate 0 |
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65 | set_interface_property clock ENABLED true |
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66 | set_interface_property clock EXPORT_OF "" |
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67 | set_interface_property clock PORT_NAME_MAP "" |
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68 | set_interface_property clock CMSIS_SVD_VARIABLES "" |
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69 | set_interface_property clock SVD_ADDRESS_GROUP "" |
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70 | |
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71 | add_interface_port clock clk clk Input 1 |
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72 | |
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73 | |
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74 | # |
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75 | # connection point reset |
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76 | # |
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77 | add_interface reset reset end |
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78 | set_interface_property reset associatedClock clock |
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79 | set_interface_property reset synchronousEdges DEASSERT |
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80 | set_interface_property reset ENABLED true |
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81 | set_interface_property reset EXPORT_OF "" |
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82 | set_interface_property reset PORT_NAME_MAP "" |
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83 | set_interface_property reset CMSIS_SVD_VARIABLES "" |
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84 | set_interface_property reset SVD_ADDRESS_GROUP "" |
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85 | |
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86 | add_interface_port reset reset reset Input 1 |
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87 | |
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88 | |
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89 | # |
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90 | # connection point ctrl |
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91 | # |
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92 | add_interface ctrl avalon end |
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93 | set_interface_property ctrl addressUnits WORDS |
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94 | set_interface_property ctrl associatedClock clock |
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95 | set_interface_property ctrl associatedReset reset |
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96 | set_interface_property ctrl bitsPerSymbol 8 |
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97 | set_interface_property ctrl burstOnBurstBoundariesOnly false |
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98 | set_interface_property ctrl burstcountUnits WORDS |
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99 | set_interface_property ctrl explicitAddressSpan 0 |
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100 | set_interface_property ctrl holdTime 0 |
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101 | set_interface_property ctrl linewrapBursts false |
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102 | set_interface_property ctrl maximumPendingReadTransactions 0 |
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103 | set_interface_property ctrl readLatency 0 |
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104 | set_interface_property ctrl readWaitTime 1 |
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105 | set_interface_property ctrl setupTime 0 |
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106 | set_interface_property ctrl timingUnits Cycles |
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107 | set_interface_property ctrl writeWaitTime 0 |
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108 | set_interface_property ctrl ENABLED true |
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109 | set_interface_property ctrl EXPORT_OF "" |
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110 | set_interface_property ctrl PORT_NAME_MAP "" |
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111 | set_interface_property ctrl CMSIS_SVD_VARIABLES "" |
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112 | set_interface_property ctrl SVD_ADDRESS_GROUP "" |
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113 | |
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114 | add_interface_port ctrl avs_ctrl_address address Input 8 |
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115 | add_interface_port ctrl avs_ctrl_read read Input 1 |
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116 | add_interface_port ctrl avs_ctrl_readdata readdata Output 32 |
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117 | add_interface_port ctrl avs_ctrl_write write Input 1 |
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118 | add_interface_port ctrl avs_ctrl_writedata writedata Input 32 |
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119 | add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1 |
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120 | set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 |
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121 | set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 |
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122 | set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 |
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123 | set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 |
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124 | |
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125 | |
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126 | # |
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127 | # connection point raw_video |
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128 | # |
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129 | add_interface raw_video avalon_streaming end |
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130 | set_interface_property raw_video associatedClock clock |
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131 | set_interface_property raw_video associatedReset reset |
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132 | set_interface_property raw_video dataBitsPerSymbol 8 |
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133 | set_interface_property raw_video errorDescriptor "" |
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134 | set_interface_property raw_video firstSymbolInHighOrderBits true |
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135 | set_interface_property raw_video maxChannel 0 |
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136 | set_interface_property raw_video readyLatency 0 |
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137 | set_interface_property raw_video ENABLED true |
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138 | set_interface_property raw_video EXPORT_OF "" |
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139 | set_interface_property raw_video PORT_NAME_MAP "" |
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140 | set_interface_property raw_video CMSIS_SVD_VARIABLES "" |
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141 | set_interface_property raw_video SVD_ADDRESS_GROUP "" |
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142 | |
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143 | add_interface_port raw_video asi_raw_video_data data Input 32 |
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144 | add_interface_port raw_video asi_raw_video_ready ready Output 1 |
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145 | add_interface_port raw_video asi_raw_video_valid valid Input 1 |
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146 | |
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147 | |
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148 | # |
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149 | # connection point raw_exg |
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150 | # |
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151 | add_interface raw_exg avalon_streaming end |
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152 | set_interface_property raw_exg associatedClock clock |
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153 | set_interface_property raw_exg associatedReset reset |
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154 | set_interface_property raw_exg dataBitsPerSymbol 8 |
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155 | set_interface_property raw_exg errorDescriptor "" |
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156 | set_interface_property raw_exg firstSymbolInHighOrderBits true |
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157 | set_interface_property raw_exg maxChannel 0 |
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158 | set_interface_property raw_exg readyLatency 0 |
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159 | set_interface_property raw_exg ENABLED true |
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160 | set_interface_property raw_exg EXPORT_OF "" |
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161 | set_interface_property raw_exg PORT_NAME_MAP "" |
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162 | set_interface_property raw_exg CMSIS_SVD_VARIABLES "" |
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163 | set_interface_property raw_exg SVD_ADDRESS_GROUP "" |
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164 | |
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165 | add_interface_port raw_exg asi_raw_exg_data data Input 32 |
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166 | add_interface_port raw_exg asi_raw_exg_ready ready Output 1 |
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167 | add_interface_port raw_exg asi_raw_exg_valid valid Input 1 |
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168 | |
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169 | |
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170 | # |
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171 | # connection point comp_video |
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172 | # |
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173 | add_interface comp_video avalon_streaming end |
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174 | set_interface_property comp_video associatedClock clock |
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175 | set_interface_property comp_video associatedReset reset |
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176 | set_interface_property comp_video dataBitsPerSymbol 8 |
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177 | set_interface_property comp_video errorDescriptor "" |
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178 | set_interface_property comp_video firstSymbolInHighOrderBits true |
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179 | set_interface_property comp_video maxChannel 0 |
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180 | set_interface_property comp_video readyLatency 0 |
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181 | set_interface_property comp_video ENABLED true |
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182 | set_interface_property comp_video EXPORT_OF "" |
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183 | set_interface_property comp_video PORT_NAME_MAP "" |
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184 | set_interface_property comp_video CMSIS_SVD_VARIABLES "" |
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185 | set_interface_property comp_video SVD_ADDRESS_GROUP "" |
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186 | |
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187 | add_interface_port comp_video asi_comp_video_data data Input 32 |
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188 | add_interface_port comp_video asi_comp_video_ready ready Output 1 |
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189 | add_interface_port comp_video asi_comp_video_valid valid Input 1 |
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190 | |
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191 | |
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192 | # |
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193 | # connection point comp_exg |
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194 | # |
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195 | add_interface comp_exg avalon_streaming end |
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196 | set_interface_property comp_exg associatedClock clock |
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197 | set_interface_property comp_exg associatedReset reset |
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198 | set_interface_property comp_exg dataBitsPerSymbol 8 |
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199 | set_interface_property comp_exg errorDescriptor "" |
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200 | set_interface_property comp_exg firstSymbolInHighOrderBits true |
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201 | set_interface_property comp_exg maxChannel 0 |
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202 | set_interface_property comp_exg readyLatency 0 |
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203 | set_interface_property comp_exg ENABLED true |
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204 | set_interface_property comp_exg EXPORT_OF "" |
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205 | set_interface_property comp_exg PORT_NAME_MAP "" |
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206 | set_interface_property comp_exg CMSIS_SVD_VARIABLES "" |
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207 | set_interface_property comp_exg SVD_ADDRESS_GROUP "" |
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208 | |
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209 | add_interface_port comp_exg asi_comp_exg_data data Input 32 |
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210 | add_interface_port comp_exg asi_comp_exg_ready ready Output 1 |
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211 | add_interface_port comp_exg asi_comp_exg_valid valid Input 1 |
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212 | |
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213 | |
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214 | # |
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215 | # connection point comp_audio |
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216 | # |
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217 | add_interface comp_audio avalon_streaming end |
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218 | set_interface_property comp_audio associatedClock clock |
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219 | set_interface_property comp_audio associatedReset reset |
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220 | set_interface_property comp_audio dataBitsPerSymbol 8 |
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221 | set_interface_property comp_audio errorDescriptor "" |
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222 | set_interface_property comp_audio firstSymbolInHighOrderBits true |
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223 | set_interface_property comp_audio maxChannel 0 |
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224 | set_interface_property comp_audio readyLatency 0 |
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225 | set_interface_property comp_audio ENABLED true |
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226 | set_interface_property comp_audio EXPORT_OF "" |
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227 | set_interface_property comp_audio PORT_NAME_MAP "" |
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228 | set_interface_property comp_audio CMSIS_SVD_VARIABLES "" |
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229 | set_interface_property comp_audio SVD_ADDRESS_GROUP "" |
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230 | |
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231 | add_interface_port comp_audio asi_comp_audio_data data Input 32 |
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232 | add_interface_port comp_audio asi_comp_audio_ready ready Output 1 |
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233 | add_interface_port comp_audio asi_comp_audio_valid valid Input 1 |
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234 | |
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