source: PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger/stream_merger_hw.tcl @ 87

# TCL File Generated by Component Editor 13.1
# Mon Mar 03 15:30:43 CET 2014
# DO NOT MODIFY


# 
# stream_merger "stream_merger" v1.0
#  2014.03.03.15:30:43
# 
# 

# 
# request TCL package from ACDS 13.1
# 
package require -exact qsys 13.1


# 
# module stream_merger
# 
set_module_property DESCRIPTION ""
set_module_property NAME stream_merger
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP smartEEG
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME stream_merger
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL stream_merger
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file stream_merger.v VERILOG PATH stream_merger.v TOP_LEVEL_FILE

add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL stream_merger
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file stream_merger.v VERILOG PATH stream_merger.v


# 
# parameters
# 


# 
# display items
# 


# 
# connection point clock
# 
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1


# 
# connection point reset
# 
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""

add_interface_port reset reset reset Input 1


# 
# connection point ctrl
# 
add_interface ctrl avalon end
set_interface_property ctrl addressUnits WORDS
set_interface_property ctrl associatedClock clock
set_interface_property ctrl associatedReset reset
set_interface_property ctrl bitsPerSymbol 8
set_interface_property ctrl burstOnBurstBoundariesOnly false
set_interface_property ctrl burstcountUnits WORDS
set_interface_property ctrl explicitAddressSpan 0
set_interface_property ctrl holdTime 0
set_interface_property ctrl linewrapBursts false
set_interface_property ctrl maximumPendingReadTransactions 0
set_interface_property ctrl readLatency 0
set_interface_property ctrl readWaitTime 1
set_interface_property ctrl setupTime 0
set_interface_property ctrl timingUnits Cycles
set_interface_property ctrl writeWaitTime 0
set_interface_property ctrl ENABLED true
set_interface_property ctrl EXPORT_OF ""
set_interface_property ctrl PORT_NAME_MAP ""
set_interface_property ctrl CMSIS_SVD_VARIABLES ""
set_interface_property ctrl SVD_ADDRESS_GROUP ""

add_interface_port ctrl avs_ctrl_address address Input 8
add_interface_port ctrl avs_ctrl_read read Input 1
add_interface_port ctrl avs_ctrl_readdata readdata Output 32
add_interface_port ctrl avs_ctrl_write write Input 1
add_interface_port ctrl avs_ctrl_writedata writedata Input 32
add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1
set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0


# 
# connection point raw_video
# 
add_interface raw_video avalon_streaming end
set_interface_property raw_video associatedClock clock
set_interface_property raw_video associatedReset reset
set_interface_property raw_video dataBitsPerSymbol 8
set_interface_property raw_video errorDescriptor ""
set_interface_property raw_video firstSymbolInHighOrderBits true
set_interface_property raw_video maxChannel 0
set_interface_property raw_video readyLatency 0
set_interface_property raw_video ENABLED true
set_interface_property raw_video EXPORT_OF ""
set_interface_property raw_video PORT_NAME_MAP ""
set_interface_property raw_video CMSIS_SVD_VARIABLES ""
set_interface_property raw_video SVD_ADDRESS_GROUP ""

add_interface_port raw_video asi_raw_video_data data Input 32
add_interface_port raw_video asi_raw_video_ready ready Output 1
add_interface_port raw_video asi_raw_video_valid valid Input 1


# 
# connection point raw_exg
# 
add_interface raw_exg avalon_streaming end
set_interface_property raw_exg associatedClock clock
set_interface_property raw_exg associatedReset reset
set_interface_property raw_exg dataBitsPerSymbol 8
set_interface_property raw_exg errorDescriptor ""
set_interface_property raw_exg firstSymbolInHighOrderBits true
set_interface_property raw_exg maxChannel 0
set_interface_property raw_exg readyLatency 0
set_interface_property raw_exg ENABLED true
set_interface_property raw_exg EXPORT_OF ""
set_interface_property raw_exg PORT_NAME_MAP ""
set_interface_property raw_exg CMSIS_SVD_VARIABLES ""
set_interface_property raw_exg SVD_ADDRESS_GROUP ""

add_interface_port raw_exg asi_raw_exg_data data Input 32
add_interface_port raw_exg asi_raw_exg_ready ready Output 1
add_interface_port raw_exg asi_raw_exg_valid valid Input 1


# 
# connection point comp_video
# 
add_interface comp_video avalon_streaming end
set_interface_property comp_video associatedClock clock
set_interface_property comp_video associatedReset reset
set_interface_property comp_video dataBitsPerSymbol 8
set_interface_property comp_video errorDescriptor ""
set_interface_property comp_video firstSymbolInHighOrderBits true
set_interface_property comp_video maxChannel 0
set_interface_property comp_video readyLatency 0
set_interface_property comp_video ENABLED true
set_interface_property comp_video EXPORT_OF ""
set_interface_property comp_video PORT_NAME_MAP ""
set_interface_property comp_video CMSIS_SVD_VARIABLES ""
set_interface_property comp_video SVD_ADDRESS_GROUP ""

add_interface_port comp_video asi_comp_video_data data Input 32
add_interface_port comp_video asi_comp_video_ready ready Output 1
add_interface_port comp_video asi_comp_video_valid valid Input 1


# 
# connection point comp_exg
# 
add_interface comp_exg avalon_streaming end
set_interface_property comp_exg associatedClock clock
set_interface_property comp_exg associatedReset reset
set_interface_property comp_exg dataBitsPerSymbol 8
set_interface_property comp_exg errorDescriptor ""
set_interface_property comp_exg firstSymbolInHighOrderBits true
set_interface_property comp_exg maxChannel 0
set_interface_property comp_exg readyLatency 0
set_interface_property comp_exg ENABLED true
set_interface_property comp_exg EXPORT_OF ""
set_interface_property comp_exg PORT_NAME_MAP ""
set_interface_property comp_exg CMSIS_SVD_VARIABLES ""
set_interface_property comp_exg SVD_ADDRESS_GROUP ""

add_interface_port comp_exg asi_comp_exg_data data Input 32
add_interface_port comp_exg asi_comp_exg_ready ready Output 1
add_interface_port comp_exg asi_comp_exg_valid valid Input 1


# 
# connection point comp_audio
# 
add_interface comp_audio avalon_streaming end
set_interface_property comp_audio associatedClock clock
set_interface_property comp_audio associatedReset reset
set_interface_property comp_audio dataBitsPerSymbol 8
set_interface_property comp_audio errorDescriptor ""
set_interface_property comp_audio firstSymbolInHighOrderBits true
set_interface_property comp_audio maxChannel 0
set_interface_property comp_audio readyLatency 0
set_interface_property comp_audio ENABLED true
set_interface_property comp_audio EXPORT_OF ""
set_interface_property comp_audio PORT_NAME_MAP ""
set_interface_property comp_audio CMSIS_SVD_VARIABLES ""
set_interface_property comp_audio SVD_ADDRESS_GROUP ""

add_interface_port comp_audio asi_comp_audio_data data Input 32
add_interface_port comp_audio asi_comp_audio_ready ready Output 1
add_interface_port comp_audio asi_comp_audio_valid valid Input 1