[83] | 1 | // synchro.v |
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| 2 | |
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| 3 | // This file was auto-generated as a prototype implementation of a module |
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| 4 | // created in component editor. It ties off all outputs to ground and |
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| 5 | // ignores all inputs. It needs to be edited to make it do something |
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| 6 | // useful. |
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| 7 | // |
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| 8 | // This file will not be automatically regenerated. You should check it in |
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| 9 | // to your version control system if you want to keep it. |
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| 10 | |
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| 11 | `timescale 1 ps / 1 ps |
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| 12 | module synchro ( |
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| 13 | input wire [7:0] avs_s0_address, // s0.address |
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| 14 | input wire avs_s0_read, // .read |
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| 15 | output wire [31:0] avs_s0_readdata, // .readdata |
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| 16 | input wire avs_s0_write, // .write |
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| 17 | input wire [31:0] avs_s0_writedata, // .writedata |
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| 18 | output wire avs_s0_waitrequest, // .waitrequest |
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| 19 | input wire clk, // clock.clk |
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| 20 | input wire reset, // reset.reset |
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| 21 | output wire video_trigger, // conduit_sync.export |
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| 22 | output wire etis_sync_clock, // .export |
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| 23 | output wire etis_sync_clock_start, // .export |
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| 24 | output wire [31:0] aso_ts_data, // ts.data |
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| 25 | input wire aso_ts_ready, // .ready |
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| 26 | output wire aso_ts_valid // .valid |
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| 27 | ); |
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| 28 | |
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| 29 | // TODO: Auto-generated HDL template |
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| 30 | |
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| 31 | assign avs_s0_waitrequest = 1'b0; |
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| 32 | |
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| 33 | assign avs_s0_readdata = 32'b00000000000000000000000000000000; |
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| 34 | |
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| 35 | assign video_trigger = 1'b0; |
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| 36 | |
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| 37 | assign etis_sync_clock_start = 1'b0; |
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| 38 | |
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| 39 | assign etis_sync_clock = 1'b0; |
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| 40 | |
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| 41 | endmodule |
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