source: PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro/synchro_hw.tcl

Last change on this file was 87, checked in by lambert, 13 years ago

Adding generation simulation support for verilog
File size: 5.0 KB
Line 
1# TCL File Generated by Component Editor 13.1
2# Mon Mar 03 15:34:33 CET 2014
3# DO NOT MODIFY
4
5
6#
7# synchro "synchro" v1.0
8# 2014.03.03.15:34:33
9#
10#
11
12#
13# request TCL package from ACDS 13.1
14#
15package require -exact qsys 13.1
16
17
18#
19# module synchro
20#
21set_module_property DESCRIPTION ""
22set_module_property NAME synchro
23set_module_property VERSION 1.0
24set_module_property INTERNAL false
25set_module_property OPAQUE_ADDRESS_MAP true
26set_module_property GROUP smartEEG
27set_module_property AUTHOR ""
28set_module_property DISPLAY_NAME synchro
29set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
30set_module_property EDITABLE true
31set_module_property ANALYZE_HDL AUTO
32set_module_property REPORT_TO_TALKBACK false
33set_module_property ALLOW_GREYBOX_GENERATION false
34
35
36#
37# file sets
38#
39add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
40set_fileset_property QUARTUS_SYNTH TOP_LEVEL synchro
41set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
42add_fileset_file synchro.v VERILOG PATH synchro.v TOP_LEVEL_FILE
43
44add_fileset SIM_VERILOG SIM_VERILOG "" ""
45set_fileset_property SIM_VERILOG TOP_LEVEL synchro
46set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
47add_fileset_file synchro.v VERILOG PATH synchro.v
48
49
50#
51# parameters
52#
53
54
55#
56# display items
57#
58
59
60#
61# connection point clock
62#
63add_interface clock clock end
64set_interface_property clock clockRate 0
65set_interface_property clock ENABLED true
66set_interface_property clock EXPORT_OF ""
67set_interface_property clock PORT_NAME_MAP ""
68set_interface_property clock CMSIS_SVD_VARIABLES ""
69set_interface_property clock SVD_ADDRESS_GROUP ""
70
71add_interface_port clock clk clk Input 1
72
73
74#
75# connection point reset
76#
77add_interface reset reset end
78set_interface_property reset associatedClock clock
79set_interface_property reset synchronousEdges DEASSERT
80set_interface_property reset ENABLED true
81set_interface_property reset EXPORT_OF ""
82set_interface_property reset PORT_NAME_MAP ""
83set_interface_property reset CMSIS_SVD_VARIABLES ""
84set_interface_property reset SVD_ADDRESS_GROUP ""
85
86add_interface_port reset reset reset Input 1
87
88
89#
90# connection point conduit_sync
91#
92add_interface conduit_sync conduit end
93set_interface_property conduit_sync associatedClock clock
94set_interface_property conduit_sync associatedReset ""
95set_interface_property conduit_sync ENABLED true
96set_interface_property conduit_sync EXPORT_OF ""
97set_interface_property conduit_sync PORT_NAME_MAP ""
98set_interface_property conduit_sync CMSIS_SVD_VARIABLES ""
99set_interface_property conduit_sync SVD_ADDRESS_GROUP ""
100
101add_interface_port conduit_sync video_trigger export Output 1
102add_interface_port conduit_sync etis_sync_clock export Output 1
103add_interface_port conduit_sync etis_sync_clock_start export Output 1
104
105
106#
107# connection point ctrl
108#
109add_interface ctrl avalon end
110set_interface_property ctrl addressUnits WORDS
111set_interface_property ctrl associatedClock clock
112set_interface_property ctrl associatedReset reset
113set_interface_property ctrl bitsPerSymbol 8
114set_interface_property ctrl burstOnBurstBoundariesOnly false
115set_interface_property ctrl burstcountUnits WORDS
116set_interface_property ctrl explicitAddressSpan 0
117set_interface_property ctrl holdTime 0
118set_interface_property ctrl linewrapBursts false
119set_interface_property ctrl maximumPendingReadTransactions 0
120set_interface_property ctrl readLatency 0
121set_interface_property ctrl readWaitTime 1
122set_interface_property ctrl setupTime 0
123set_interface_property ctrl timingUnits Cycles
124set_interface_property ctrl writeWaitTime 0
125set_interface_property ctrl ENABLED true
126set_interface_property ctrl EXPORT_OF ""
127set_interface_property ctrl PORT_NAME_MAP ""
128set_interface_property ctrl CMSIS_SVD_VARIABLES ""
129set_interface_property ctrl SVD_ADDRESS_GROUP ""
130
131add_interface_port ctrl avs_s0_address address Input 8
132add_interface_port ctrl avs_s0_read read Input 1
133add_interface_port ctrl avs_s0_readdata readdata Output 32
134add_interface_port ctrl avs_s0_write write Input 1
135add_interface_port ctrl avs_s0_writedata writedata Input 32
136add_interface_port ctrl avs_s0_waitrequest waitrequest Output 1
137set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
138set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
139set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
140set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
141
142
143#
144# connection point ts
145#
146add_interface ts avalon_streaming start
147set_interface_property ts associatedClock clock
148set_interface_property ts associatedReset reset
149set_interface_property ts dataBitsPerSymbol 8
150set_interface_property ts errorDescriptor ""
151set_interface_property ts firstSymbolInHighOrderBits true
152set_interface_property ts maxChannel 0
153set_interface_property ts readyLatency 0
154set_interface_property ts ENABLED true
155set_interface_property ts EXPORT_OF ""
156set_interface_property ts PORT_NAME_MAP ""
157set_interface_property ts CMSIS_SVD_VARIABLES ""
158set_interface_property ts SVD_ADDRESS_GROUP ""
159
160add_interface_port ts aso_ts_data data Output 32
161add_interface_port ts aso_ts_ready ready Input 1
162add_interface_port ts aso_ts_valid valid Output 1
163
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