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source: PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro/synchro_hw.tcl @ 84

Last change on this file since 84 was 84, checked in by lambert, 10 years ago
Adding hierarchical subdirectory for every component
File size: 4.8 KB

Line
1	# TCL File Generated by Component Editor 13.1
2	# Fri Feb 28 17:08:14 CET 2014
3	# DO NOT MODIFY
4
5
6	#
7	# synchro "synchro" v1.0
8	# 2014.02.28.17:08:14
9	#
10	#
11
12	#
13	# request TCL package from ACDS 13.1
14	#
15	package require -exact qsys 13.1
16
17
18	#
19	# module synchro
20	#
21	set_module_property DESCRIPTION ""
22	set_module_property NAME synchro
23	set_module_property VERSION 1.0
24	set_module_property INTERNAL false
25	set_module_property OPAQUE_ADDRESS_MAP true
26	set_module_property GROUP smartEEG
27	set_module_property AUTHOR ""
28	set_module_property DISPLAY_NAME synchro
29	set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
30	set_module_property EDITABLE true
31	set_module_property ANALYZE_HDL AUTO
32	set_module_property REPORT_TO_TALKBACK false
33	set_module_property ALLOW_GREYBOX_GENERATION false
34
35
36	#
37	# file sets
38	#
39	add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
40	set_fileset_property QUARTUS_SYNTH TOP_LEVEL synchro
41	set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
42	add_fileset_file synchro.v VERILOG PATH synchro.v TOP_LEVEL_FILE
43
44
45	#
46	# parameters
47	#
48
49
50	#
51	# display items
52	#
53
54
55	#
56	# connection point clock
57	#
58	add_interface clock clock end
59	set_interface_property clock clockRate 0
60	set_interface_property clock ENABLED true
61	set_interface_property clock EXPORT_OF ""
62	set_interface_property clock PORT_NAME_MAP ""
63	set_interface_property clock CMSIS_SVD_VARIABLES ""
64	set_interface_property clock SVD_ADDRESS_GROUP ""
65
66	add_interface_port clock clk clk Input 1
67
68
69	#
70	# connection point reset
71	#
72	add_interface reset reset end
73	set_interface_property reset associatedClock clock
74	set_interface_property reset synchronousEdges DEASSERT
75	set_interface_property reset ENABLED true
76	set_interface_property reset EXPORT_OF ""
77	set_interface_property reset PORT_NAME_MAP ""
78	set_interface_property reset CMSIS_SVD_VARIABLES ""
79	set_interface_property reset SVD_ADDRESS_GROUP ""
80
81	add_interface_port reset reset reset Input 1
82
83
84	#
85	# connection point conduit_sync
86	#
87	add_interface conduit_sync conduit end
88	set_interface_property conduit_sync associatedClock clock
89	set_interface_property conduit_sync associatedReset ""
90	set_interface_property conduit_sync ENABLED true
91	set_interface_property conduit_sync EXPORT_OF ""
92	set_interface_property conduit_sync PORT_NAME_MAP ""
93	set_interface_property conduit_sync CMSIS_SVD_VARIABLES ""
94	set_interface_property conduit_sync SVD_ADDRESS_GROUP ""
95
96	add_interface_port conduit_sync video_trigger export Output 1
97	add_interface_port conduit_sync etis_sync_clock export Output 1
98	add_interface_port conduit_sync etis_sync_clock_start export Output 1
99
100
101	#
102	# connection point ctrl
103	#
104	add_interface ctrl avalon end
105	set_interface_property ctrl addressUnits WORDS
106	set_interface_property ctrl associatedClock clock
107	set_interface_property ctrl associatedReset reset
108	set_interface_property ctrl bitsPerSymbol 8
109	set_interface_property ctrl burstOnBurstBoundariesOnly false
110	set_interface_property ctrl burstcountUnits WORDS
111	set_interface_property ctrl explicitAddressSpan 0
112	set_interface_property ctrl holdTime 0
113	set_interface_property ctrl linewrapBursts false
114	set_interface_property ctrl maximumPendingReadTransactions 0
115	set_interface_property ctrl readLatency 0
116	set_interface_property ctrl readWaitTime 1
117	set_interface_property ctrl setupTime 0
118	set_interface_property ctrl timingUnits Cycles
119	set_interface_property ctrl writeWaitTime 0
120	set_interface_property ctrl ENABLED true
121	set_interface_property ctrl EXPORT_OF ""
122	set_interface_property ctrl PORT_NAME_MAP ""
123	set_interface_property ctrl CMSIS_SVD_VARIABLES ""
124	set_interface_property ctrl SVD_ADDRESS_GROUP ""
125
126	add_interface_port ctrl avs_s0_address address Input 8
127	add_interface_port ctrl avs_s0_read read Input 1
128	add_interface_port ctrl avs_s0_readdata readdata Output 32
129	add_interface_port ctrl avs_s0_write write Input 1
130	add_interface_port ctrl avs_s0_writedata writedata Input 32
131	add_interface_port ctrl avs_s0_waitrequest waitrequest Output 1
132	set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
133	set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
134	set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
135	set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
136
137
138	#
139	# connection point ts
140	#
141	add_interface ts avalon_streaming start
142	set_interface_property ts associatedClock clock
143	set_interface_property ts associatedReset reset
144	set_interface_property ts dataBitsPerSymbol 8
145	set_interface_property ts errorDescriptor ""
146	set_interface_property ts firstSymbolInHighOrderBits true
147	set_interface_property ts maxChannel 0
148	set_interface_property ts readyLatency 0
149	set_interface_property ts ENABLED true
150	set_interface_property ts EXPORT_OF ""
151	set_interface_property ts PORT_NAME_MAP ""
152	set_interface_property ts CMSIS_SVD_VARIABLES ""
153	set_interface_property ts SVD_ADDRESS_GROUP ""
154
155	add_interface_port ts aso_ts_data data Output 32
156	add_interface_port ts aso_ts_ready ready Input 1
157	add_interface_port ts aso_ts_valid valid Output 1
158

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