source: PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro @ 89

Name Size Rev Age Author Last Change
../
synchro.v 2.3 KB ​ 89   11 years szahmed Added Headline comments for Verilog files explaining their brief …
synchro_hw.tcl 5.0 KB ​ 87   11 years lambert Adding generation simulation support for verilog
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