Changeset 89 for PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro

Timestamp:

Mar 3, 2014, 4:47:59 PM (11 years ago)

Author:

szahmed

Message:

Added Headline comments for Verilog files explaining their brief properties, version number etc.

File:

• PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro/synchro.v (modified) (2 diffs)

PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro/synchro.v

@@ -1 @@
-// synchro.v
-
-// This file was auto-generated as a prototype implementation of a module
-// created in component editor.  It ties off all outputs to ground and
-// ignores all inputs.  It needs to be edited to make it do something
-// useful.
-// 
-// This file will not be automatically regenerated.  You should check it in
-// to your version control system if you want to keep it.
+/********************************************************************
+ *                    COPYRIGHT LIP6 2014
+ *-----------------------------------------------------------------*/
+/** 
+ * @file    synchro.v
+ * @brief   Creats video trigger, time-stamp/sync clock and rest signal (for ETIS)
+ *
+ * This module generates the Video trigger signal for the Camera at the choosen fps. It also generates the time-stamp/sync clock that is
+ * used by both Acquision (ETIS) and Compression (Lip6) boards for time-stamp counters along with a start signal whic resets the time-stamp
+ * counters when the acquisition start command comes from PC (Acacia). The value of time-stamp register is transmitted to the Video coder via AvalonST source 
+ *
+ * @author  S. Z. Ahmed         <syed-zahid.ahmed@lip6.fr>
+ * @author  L. Lambert          <laurent.lambert@lip6.fr>
+ * @date    Fri. 28 Feb. 2014
+ * 
+ * Revision History
+ * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
+ *
+ *******************************************************************/
 
 `timescale 1 ps / 1 ps
 module synchro (
-                input  wire [7:0]  avs_s0_address,        //           s0.address
-                input  wire        avs_s0_read,           //             .read
-                output wire [31:0] avs_s0_readdata,       //             .readdata
-                input  wire        avs_s0_write,          //             .write
-                input  wire [31:0] avs_s0_writedata,      //             .writedata
-                output wire        avs_s0_waitrequest,    //             .waitrequest
+                input  wire [7:0]  avs_ctrl_address,        //           ctrl.address
+                input  wire        avs_ctrl_read,           //             .read
+                output wire [31:0] avs_ctrl_readdata,       //             .readdata
+                input  wire        avs_ctrl_write,          //             .write
+                input  wire [31:0] avs_ctrl_writedata,      //             .writedata
+                output wire        avs_ctrl_waitrequest,    //             .waitrequest
                 input  wire        clk,                   //        clock.clk
                 input  wire        reset,                 //        reset.reset
@@ -29 +39 @@
         // TODO: Auto-generated HDL template
 
-        assign avs_s0_waitrequest = 1'b0;
+        assign avs_ctrl_waitrequest = 1'b0;
 
-        assign avs_s0_readdata = 32'b00000000000000000000000000000000;
+        assign avs_ctrl_readdata = 32'b00000000000000000000000000000000;
 
         assign video_trigger = 1'b0;