[89] | 1 | /******************************************************************** |
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| 2 | * COPYRIGHT LIP6 2014 |
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| 3 | *-----------------------------------------------------------------*/ |
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| 4 | /** |
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| 5 | * @file video_codec.v |
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| 6 | * @brief Performs Video Compression and Downscaled raw video bypass |
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| 7 | * |
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| 8 | * This module receives the RAW video data from Frame Grabber via AvalonST sink. It performs Video Compression and Downscaled RAW video bypass (for live preview), |
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| 9 | * it adds time-stamp to the video frames that is received via AvalonST sink from synchro module. It transmitts the RAW and Compressed Data to stream merger via AvalonST sources |
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| 10 | * |
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| 11 | * @author S. Z. Ahmed <syed-zahid.ahmed@lip6.fr> |
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| 12 | * @author L. Lambert <laurent.lambert@lip6.fr> |
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| 13 | * @date Fri. 28 Feb. 2014 |
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| 14 | * |
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| 15 | * Revision History |
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| 16 | * @version V1.0 Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui} |
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| 17 | * |
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| 18 | *******************************************************************/ |
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[83] | 19 | |
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| 20 | `timescale 1 ps / 1 ps |
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| 21 | module video_codec #( |
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| 22 | parameter AUTO_CLOCK_CLOCK_RATE = "-1" |
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| 23 | ) ( |
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| 24 | input wire clk, // clock.clk |
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| 25 | input wire reset, // reset.reset |
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| 26 | input wire [7:0] avs_ctrl_address, // ctrl.address |
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| 27 | input wire avs_ctrl_read, // .read |
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| 28 | output wire [31:0] avs_ctrl_readdata, // .readdata |
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| 29 | input wire avs_ctrl_write, // .write |
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| 30 | input wire [31:0] avs_ctrl_writedata, // .writedata |
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| 31 | output wire avs_ctrl_waitrequest, // .waitrequest |
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| 32 | input wire [31:0] asi_raw_video_data, // raw_video.data |
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| 33 | output wire asi_raw_video_ready, // .ready |
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| 34 | input wire asi_raw_video_valid, // .valid |
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| 35 | input wire aso_raw_video_ds_ready, // raw_video_ds.ready |
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| 36 | output wire aso_raw_video_ds_valid, // .valid |
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| 37 | output wire [31:0] aso_raw_video_ds_data, // .data |
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| 38 | input wire aso_comp_video_ready, // comp_video.ready |
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| 39 | output wire aso_comp_video_valid, // .valid |
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| 40 | output wire [31:0] aso_comp_video_data, // .data |
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| 41 | input wire [31:0] asi_ts_data, // ts.data |
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| 42 | output wire asi_ts_ready, // .ready |
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| 43 | input wire asi_ts_valid // .valid |
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| 44 | ); |
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| 45 | |
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| 46 | // TODO: Auto-generated HDL template |
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| 47 | |
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| 48 | assign avs_s0_waitrequest = 1'b0; |
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| 49 | |
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| 50 | assign avs_s0_readdata = 32'b00000000000000000000000000000000; |
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| 51 | |
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| 52 | assign asi_in0_ready = 1'b0; |
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| 53 | |
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| 54 | assign aso_out0_valid = 1'b0; |
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| 55 | |
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| 56 | assign aso_out0_data = 32'b00000000000000000000000000000000; |
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| 57 | |
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| 58 | endmodule |
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