Changeset 135

Timestamp:

Apr 8, 2014, 5:45:26 PM (11 years ago)

Author:

rolagamo

Message:

 

Location:

PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC

Files:

• Def_Request.vhd (added)
• SCHEDULER4_4.VHD (modified) (2 diffs)

PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/SCHEDULER4_4.VHD

@@ -49 +49 @@
         Grant,East,South : out  STD_LOGIC );
 End Component;--Signaux de connexion des cellues
-
+component Def_Request is
+generic (NB_IO :positive:=4);
+    Port ( Req : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+                          fifo_full : in STD_LOGIC_VECTOR (NB_IO downto 1);
+           priority_rotation : in  STD_LOGIC_VECTOR (NB_IO downto 1);
+           grant : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           request : out  STD_LOGIC_VECTOR (NB_IO**2 downto 1));
+end component;
 constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S
 
@@ -58 +67 @@
 SIGNAL Signal_priority  : STD_LOGIC_VECTOR (7 DOWNTO 1);--signal pour la connection des vecteur de priorité
 SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
- Signal Fifo_out_full :  STD_LOGIC_VECTOR (NB_IO downto 1);
- signal grant_latch : std_logic_vector(NB_IO2 downto 1); 
+-- Signal Fifo_out_full :  STD_LOGIC_VECTOR (NB_IO downto 1);
+-- signal grant_latch : std_logic_vector(NB_IO2 downto 1); 
  signal priority_rotation_en : std_logic; 
-signal Grant,request,req_grant,Grant_bak :  std_logic_vector(NB_IO2 downto 1):=(others=>'0');
- signal Mreq :  std_logic_vector(NB_IO2 downto 1):=(others=>'1');
+signal Grant,request :  std_logic_vector(NB_IO2 downto 1):=(others=>'0');
+-- signal Mreq :  std_logic_vector(NB_IO2 downto 1):=(others=>'1');
 
  begin
 
---validation de la rotation de priorité lorsque aucun port n'emet 
- req_grant<=(req and grant );
+----validation de la rotation de priorité lorsque aucun port n'emet 
+-- req_grant<=(req and grant );
  priority_rotation_en <= '1' when   unsigned(priority_rotation) = 2**NB_IO-1 else       '0'; 
-request<=req and mreq;
---latch  qui memorise le signal grant pendant la transmission 
-grant_latch_process : process(clk)
-  begin 
-  if rising_edge(clk) then 
-   if reset = '1' then 
-                grant_latch <= (others => '0');
-                Fifo_out_full<=(others => '0');
-         elsif priority_rotation_en = '1' or unsigned(req_grant)=0 then 
-           grant_latch <= Grant;
-           Fifo_out_full<=fifo_full;
-  else
-         grant_latch <= Grant; 
-         Fifo_out_full<=fifo_full; 
-   end if; 
-   end if; 
-
- end process; 
- def_mreq: process(grant_latch,fifo_full)
-
-variable t:std_logic_vector(NB_IO2 downto 1):=(others=>'0');
-begin 
-    
-  for i in 0 to NB_IO2-1 loop
-    t(i+1):='0';
-    --sur le front montant de fifo_full sauver l'état Grant courant 
-    if fifo_full(i mod NB_IO+1)='1' and  fifo_out_full(i mod NB_IO+1)='0' then
-      Grant_bak(i+1)<= grant_latch(i+1);
-    elsif fifo_full(i mod NB_IO+1)='0' and  fifo_out_full(i mod NB_IO+1)='0'  then
-      Grant_bak(i+1)<='0';
-    end if;
-  for j in 0 to NB_IO-1 loop
-    t(i+1):=t(i+1) or grant_latch(j*NB_IO+1+i mod NB_IO) or fifo_out_full(i mod NB_IO+1);
-    
-  end loop;
-      mreq(i+1)<=not(t(i+1) ) or grant_latch(i+1)or grant_bak(i+1);    
-  end loop;
-end process;
+--request<=req and mreq;
+----latch  qui memorise le signal grant pendant la transmission 
+--grant_latch_process : process(clk)
+--  begin 
+--  if rising_edge(clk) then 
+--   if reset = '1' then 
+--              grant_latch <= (others => '0');
+--              Fifo_out_full<=(others => '0');
+--       elsif priority_rotation_en = '1' or unsigned(req_grant)=0 then 
+--         grant_latch <= Grant;
+--         Fifo_out_full<=fifo_full;
+--  else
+--       grant_latch <= Grant; 
+--       Fifo_out_full<=fifo_full; 
+--   end if; 
+--   end if; 
+--
+-- end process; 
+-- def_mreq: process(grant_latch,fifo_full)
+--
+--variable t:std_logic_vector(NB_IO2 downto 1):=(others=>'0');
+--begin 
+--    
+--  for i in 0 to NB_IO2-1 loop
+--    t(i+1):='0';
+--    --sur le front montant de fifo_full sauver l'état Grant courant 
+--    if fifo_full(i mod NB_IO+1)='1' and  fifo_out_full(i mod NB_IO+1)='0' then
+--      Grant_bak(i+1)<= grant_latch(i+1);
+--    elsif fifo_full(i mod NB_IO+1)='0' and  fifo_out_full(i mod NB_IO+1)='0'  then
+--      Grant_bak(i+1)<='0';
+--    end if;
+--  for j in 0 to NB_IO-1 loop
+--    t(i+1):=t(i+1) or grant_latch(j*NB_IO+1+i mod NB_IO) or fifo_out_full(i mod NB_IO+1);
+--    
+--  end loop;
+--      mreq(i+1)<=not(t(i+1) ) or grant_latch(i+1)or grant_bak(i+1);    
+--  end loop;
+--end process;
+--cette instance permet de déterminer le vecteur request en fonction de l'état fifo_full et de la requête initiale
+inst_defreq: def_request generic map (NB_IO=>4)
+port map (clk=>clk,
+reset=>reset,
+req=>req,
+fifo_full=>fifo_full,
+priority_rotation=>priority_rotation,
+grant=>grant,
+request=>request
+);
+
  port_grant <=  grant; 
  Grant(1)  <= Signal_grant(1)(1) or Signal_grant(5)(1); --  Grant(1,1)