Ignore:
Timestamp:
Apr 9, 2014, 11:19:58 PM (10 years ago)
Author:
rolagamo
Message:
 
Location:
PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs
Files:
2 edited

Legend:

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  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs/cg.xmsgs

    r115 r137  
    66     users do not edit the contents of this file. -->
    77<messages>
    8 <msg type="info" file="sim" num="0" delta="new" >Generating component instance &apos;<arg fmt="%s" index="1">mem_4k8</arg>&apos; of &apos;<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>&apos; from &apos;<arg fmt="%s" index="3">C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>&apos;.
     8<msg type="info" file="sim" num="0" delta="new" >Generating component instance &apos;<arg fmt="%s" index="1">mem8k8</arg>&apos; of &apos;<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>&apos; from &apos;<arg fmt="%s" index="3">C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>&apos;.
     9</msg>
     10
     11<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;mem8k8&apos; already exists in the project. Output products for this core may be overwritten.</arg>
     12</msg>
     13
     14<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for &apos;mem8k8&apos;...</arg>
     15</msg>
     16
     17<msg type="info" file="sim" num="0" delta="new" >Finished generation of ASY schematic symbol.
     18</msg>
     19
     20<msg type="info" file="sim" num="0" delta="new" >Finished FLIST file generation.
    921</msg>
    1022

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs/pn_parser.xmsgs

    r115 r137  
    99
    1010<messages>
    11 <msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/MPI_HCL/Test_Timer/ipcore_dir/mem_4k8.vhd&quot; into library work</arg>
     11<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/MPI_HCL/Test_Timer/ipcore_dir/mem8k8.vhd&quot; into library work</arg>
    1212</msg>
    1313
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