- Timestamp:
- Apr 9, 2014, 11:19:58 PM (10 years ago)
- Location:
- PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
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PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs/cg.xmsgs
r115 r137 6 6 users do not edit the contents of this file. --> 7 7 <messages> 8 <msg type="info" file="sim" num="0" delta="new" >Generating component instance '<arg fmt="%s" index="1">mem_4k8</arg>' of '<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>' from '<arg fmt="%s" index="3">C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>'. 8 <msg type="info" file="sim" num="0" delta="new" >Generating component instance '<arg fmt="%s" index="1">mem8k8</arg>' of '<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>' from '<arg fmt="%s" index="3">C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>'. 9 </msg> 10 11 <msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'mem8k8' already exists in the project. Output products for this core may be overwritten.</arg> 12 </msg> 13 14 <msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for 'mem8k8'...</arg> 15 </msg> 16 17 <msg type="info" file="sim" num="0" delta="new" >Finished generation of ASY schematic symbol. 18 </msg> 19 20 <msg type="info" file="sim" num="0" delta="new" >Finished FLIST file generation. 9 21 </msg> 10 22 -
PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs/pn_parser.xmsgs
r115 r137 9 9 10 10 <messages> 11 <msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "D:/MPI_HCL/Test_Timer/ipcore_dir/mem _4k8.vhd" into library work</arg>11 <msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "D:/MPI_HCL/Test_Timer/ipcore_dir/mem8k8.vhd" into library work</arg> 12 12 </msg> 13 13
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