Ignore:
Timestamp:
Apr 9, 2014, 11:19:58 PM (10 years ago)
Author:
rolagamo
Message:
 
File:
1 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.xco

    r115 r137  
    22#
    33# Xilinx Core Generator version 13.3
    4 # Date: Mon Mar 03 16:26:23 2014
     4# Date: Wed Apr 09 13:43:42 2014
    55#
    66##############################################################
    … …  
    2323SET createndf = false
    2424SET designentry = VHDL
    25 SET device = xc6slx45
    26 SET devicefamily = spartan6
     25SET device = xc7a100t
     26SET devicefamily = artix7
    2727SET flowvendor = Other
    2828SET formalverification = false
    … …  
    103103# END Extra information
    104104GENERATE
    105 # CRC: c197a96c
     105# CRC:  7a5cdcc
Note: See TracChangeset for help on using the changeset viewer.