Changeset 139 for PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Crossbar.vhd
- Timestamp:
- May 21, 2014, 11:36:19 AM (10 years ago)
- Location:
- PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0
- Files:
-
- 1 edited
- 2 copied
Legend:
- Unmodified
- Added
- Removed
-
PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Crossbar.vhd
r101 r139 38 38 Port ( clk : in STD_LOGIC; 39 39 reset : in STD_LOGIC; --pour gérer le pipeline 40 Port1_in : in STD_LOGIC_VECTOR ( Word-1downto 0);41 Port2_in : in STD_LOGIC_VECTOR ( Word-1downto 0);42 Port3_in : in STD_LOGIC_VECTOR ( Word-1downto 0);43 Port4_in : in STD_LOGIC_VECTOR ( Word-1downto 0);44 Port5_in : in STD_LOGIC_VECTOR ( Word-1downto 0);45 Port6_in : in STD_LOGIC_VECTOR ( Word-1downto 0);46 Port7_in : in STD_LOGIC_VECTOR ( Word-1downto 0);47 Port8_in : in STD_LOGIC_VECTOR ( Word-1downto 0);48 Port9_in : in STD_LOGIC_VECTOR ( Word-1downto 0);49 Port10_in : in STD_LOGIC_VECTOR ( Word-1downto 0);50 Port11_in : in STD_LOGIC_VECTOR ( Word-1downto 0);51 Port12_in : in STD_LOGIC_VECTOR ( Word-1downto 0);52 Port13_in : in STD_LOGIC_VECTOR ( Word-1downto 0);53 Port14_in : in STD_LOGIC_VECTOR ( Word-1downto 0);54 Port15_in : in STD_LOGIC_VECTOR ( Word-1downto 0);55 Port16_in : in STD_LOGIC_VECTOR ( Word-1downto 0);40 Port1_in : in STD_LOGIC_VECTOR (7 downto 0); 41 Port2_in : in STD_LOGIC_VECTOR (7 downto 0); 42 Port3_in : in STD_LOGIC_VECTOR (7 downto 0); 43 Port4_in : in STD_LOGIC_VECTOR (7 downto 0); 44 Port5_in : in STD_LOGIC_VECTOR (7 downto 0); 45 Port6_in : in STD_LOGIC_VECTOR (7 downto 0); 46 Port7_in : in STD_LOGIC_VECTOR (7 downto 0); 47 Port8_in : in STD_LOGIC_VECTOR (7 downto 0); 48 Port9_in : in STD_LOGIC_VECTOR (7 downto 0); 49 Port10_in : in STD_LOGIC_VECTOR (7 downto 0); 50 Port11_in : in STD_LOGIC_VECTOR (7 downto 0); 51 Port12_in : in STD_LOGIC_VECTOR (7 downto 0); 52 Port13_in : in STD_LOGIC_VECTOR (7 downto 0); 53 Port14_in : in STD_LOGIC_VECTOR (7 downto 0); 54 Port15_in : in STD_LOGIC_VECTOR (7 downto 0); 55 Port16_in : in STD_LOGIC_VECTOR (7 downto 0); 56 56 57 57 Port1_pulse_in : in std_logic; … … 89 89 Port16_pulse_out : out std_logic; 90 90 91 Port1_out : out STD_LOGIC_VECTOR ( Word-1downto 0);92 Port2_out : out STD_LOGIC_VECTOR ( Word-1downto 0);93 Port3_out : out STD_LOGIC_VECTOR ( Word-1downto 0);94 Port4_out : out STD_LOGIC_VECTOR ( Word-1downto 0);95 Port5_out : out STD_LOGIC_VECTOR ( Word-1downto 0);96 Port6_out : out STD_LOGIC_VECTOR ( Word-1downto 0);97 Port7_out : out STD_LOGIC_VECTOR ( Word-1downto 0);98 Port8_out : out STD_LOGIC_VECTOR ( Word-1downto 0);99 Port9_out : out STD_LOGIC_VECTOR ( Word-1downto 0);100 Port10_out : out STD_LOGIC_VECTOR ( Word-1downto 0);101 Port11_out : out STD_LOGIC_VECTOR ( Word-1downto 0);102 Port12_out : out STD_LOGIC_VECTOR ( Word-1downto 0);103 Port13_out : out STD_LOGIC_VECTOR ( Word-1downto 0);104 Port14_out : out STD_LOGIC_VECTOR ( Word-1downto 0);105 Port15_out : out STD_LOGIC_VECTOR ( Word-1downto 0);106 Port16_out : out STD_LOGIC_VECTOR ( Word-1downto 0);91 Port1_out : out STD_LOGIC_VECTOR (7 downto 0); 92 Port2_out : out STD_LOGIC_VECTOR (7 downto 0); 93 Port3_out : out STD_LOGIC_VECTOR (7 downto 0); 94 Port4_out : out STD_LOGIC_VECTOR (7 downto 0); 95 Port5_out : out STD_LOGIC_VECTOR (7 downto 0); 96 Port6_out : out STD_LOGIC_VECTOR (7 downto 0); 97 Port7_out : out STD_LOGIC_VECTOR (7 downto 0); 98 Port8_out : out STD_LOGIC_VECTOR (7 downto 0); 99 Port9_out : out STD_LOGIC_VECTOR (7 downto 0); 100 Port10_out : out STD_LOGIC_VECTOR (7 downto 0); 101 Port11_out : out STD_LOGIC_VECTOR (7 downto 0); 102 Port12_out : out STD_LOGIC_VECTOR (7 downto 0); 103 Port13_out : out STD_LOGIC_VECTOR (7 downto 0); 104 Port14_out : out STD_LOGIC_VECTOR (7 downto 0); 105 Port15_out : out STD_LOGIC_VECTOR (7 downto 0); 106 Port16_out : out STD_LOGIC_VECTOR (7 downto 0); 107 107 108 108 Ctrl : in STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1)
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