Changeset 139 for PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SCHEDULER9_9.VHD

Timestamp:

May 21, 2014, 11:36:19 AM (10 years ago)

Author:

rolagamo

Message:

Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC

Location:

PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0

Files:

• . (copied) (copied from PROJECT_CORE_MPI/MPI_HCL/TRUNK)
• NOC (copied) (copied from PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC)
• NOC/SCHEDULER9_9.VHD (modified) (3 diffs)

PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SCHEDULER9_9.VHD

@@ -30 +30 @@
 --use UNISIM.VComponents.all;
 entity Scheduler9_9 is
-    Port ( Request : in  STD_LOGIC_VECTOR (81 downto 1);
+    Port ( Req : in  STD_LOGIC_VECTOR (81 downto 1);
                    Fifo_full : in STD_LOGIC_VECTOR (9 downto 1);
            clk : in  STD_LOGIC;
@@ -39 +39 @@
 
 architecture Behavioral of Scheduler9_9 is
+ --déclaration de constantes 
+Constant NB_IO : positive:=9; --le nombre de ports d'entrée/sortie
 --Declaration du types
 --tableau de signaux de connexion des cellules arbitres
-TYPE C_Bar_Signal_Array IS ARRAY(17 downto 1) of STD_LOGIC_VECTOR(9 downto 1);
+TYPE C_Bar_Signal_Array IS ARRAY(NB_IO*2-1 downto 1) of STD_LOGIC_VECTOR(NB_IO downto 1);
 -- declaration du composant cellule d'arbitrage
 Component Arbiter 
   PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
         Grant,East,South : out  STD_LOGIC );
-End Component;--Signaux de connexion des cellues
+End Component;
+component Def_Request is
+generic (NB_IO :positive:=9);
+    Port ( Req : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+                          fifo_full : in STD_LOGIC_VECTOR (NB_IO downto 1);
+           priority_rotation : in  STD_LOGIC_VECTOR (NB_IO downto 1);
+           grant : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           request : out  STD_LOGIC_VECTOR (NB_IO**2 downto 1));
+end component;
+constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S
+
+--Signaux de connexion des cellues
 SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
 SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
@@ -53 +68 @@
 SIGNAL Signal_priority  : STD_LOGIC_VECTOR (17 DOWNTO 1);--signal pour la connection des vecteur de priorité
 SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
- signal grant_latch : std_logic_vector(81 downto 1); 
+
  signal priority_rotation_en : std_logic; 
- signal Grant :  std_logic_vector(81 downto 1);
+signal Grant,request :  std_logic_vector(NB_IO2 downto 1):=(others=>'0');
  begin
 
 --validation de la rotation de priorité lorsque aucun port n'emet 
- priority_rotation_en <= '1' when unsigned(priority_rotation) = 511 else        '0'; 
---latch servant qui memorise le signal grant pendant a transmission 
-grant_latch_process : process(clk)
- begin 
-  if rising_edge(clk) then 
-   if reset = '1' then 
-                grant_latch <= (others => '0'); 
-         elsif priority_rotation_en = '1' then 
-           grant_latch <= Grant; 
-   end if; 
-   end if; 
- end process; 
- port_grant <= Grant and grant_latch; 
+-- priority_rotation_en <= '1' when unsigned(priority_rotation) = 511 else      '0';tation) = 511 else  '0'; 
+ priority_rotation_en <= '1' when   unsigned(priority_rotation) = 2**NB_IO-1 else       '0'; 
+--evaluation du signal request
+inst_defreq: def_request generic map (NB_IO=>9)
+port map (clk=>clk,
+reset=>reset,
+req=>req,
+fifo_full=>fifo_full,
+priority_rotation=>priority_rotation,
+grant=>grant,
+request=>request
+);
+
+ port_grant <=  grant; 
  Grant(1)  <= Signal_grant(1)(1) or Signal_grant(10)(1); --  Grant(1,1)
 Grant(2)  <= Signal_grant(2)(2) or Signal_grant(11)(2); --  Grant(1,2)