Changeset 139 for PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/Test_Timer/wave.do

Timestamp:

May 21, 2014, 11:36:19 AM (10 years ago)

Author:

rolagamo

Message:

Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC

Location:

PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0

Files:

• . (copied) (copied from PROJECT_CORE_MPI/MPI_HCL/TRUNK)
• Test_Timer/wave.do (modified) (2 diffs)

PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/Test_Timer/wave.do

@@ -1 +1 @@
 onerror {resume}
 quietly WaveActivateNextPane {} 0
-add wave -noupdate /mpi_test/clk
-add wave -noupdate /mpi_test/reset
-add wave -noupdate /mpi_test/result
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_in
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_out
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_rd
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_wr
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ram_address
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_in
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_out
-add wave -noupdate /mpi_test/clk
-add wave -noupdate /mpi_test/reset
-add wave -noupdate /mpi_test/result
-add wave -noupdate /mpi_test/clk
-add wave -noupdate /mpi_test/reset
-add wave -noupdate /mpi_test/result
-add wave -noupdate /mpi_test/clk
-add wave -noupdate /mpi_test/reset
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/src_address
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_data
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_wr_en
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/dma_rd_grant
-add wave -noupdate /mpi_test/result
-add wave -noupdate /mpi_test/clk
-add wave -noupdate /mpi_test/reset
-add wave -noupdate /mpi_test/result
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_rd
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_wr
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_whole
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_done
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_BitMask
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_BitVal
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_address
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_in
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_out
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_rd
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_wr
-add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/RunState
-add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/ct_state
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/ex1_state
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_data
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/fifo_src
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/Snd_Start
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/Snd_Start
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/stInit2
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/etcmd
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/etrec
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/port_out_data
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/port_out_data_available
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/snd_start_i
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_data
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/n
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_wr_en
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/fifo_data_out
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/p_len
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/fifo_rd_en
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/fifo_empty
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
-add wave -noupdate -radix unsigned /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/P_len
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_data_available
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/dest_address
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/P_len
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/n
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/State
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_in
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_out
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/n
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/n_i
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/P_len
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/P_len_i
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_wr_request
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_wr_grant
-add wave -noupdate /mpi_test/result
-add wave -noupdate -expand -subitemconfig {/mpi_test/uut/PE_s(1)/S/HT_task/sram.O {-height 18 -childformat {{/mpi_test/uut/PE_s(1)/S/HT_task/sram.O.addr_wr -radix hexadecimal} {/mpi_test/uut/PE_s(1)/S/HT_task/sram.O.addr_rd -radix hexadecimal} {/mpi_test/uut/PE_s(1)/S/HT_task/sram.O.data_in -radix hexadecimal}} -expand} /mpi_test/uut/PE_s(1)/S/HT_task/sram.O.addr_wr {-height 18 -radix hexadecimal} /mpi_test/uut/PE_s(1)/S/HT_task/sram.O.addr_rd {-height 18 -radix hexadecimal} /mpi_test/uut/PE_s(1)/S/HT_task/sram.O.data_in {-height 18 -radix hexadecimal} /mpi_test/uut/PE_s(1)/S/HT_task/sram.I -expand} /mpi_test/uut/PE_s(1)/S/HT_task/sram
-add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/Libr
-add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/RunState
-add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/ct_state
-add wave -noupdate /mpi_test/uut/PE_s(2)/S/HT_task/RunState
-add wave -noupdate /mpi_test/uut/PE_s(2)/S/HT_task/ct_state
-add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/HT_task/sram.O.addr_rd
-add wave -noupdate /mpi_test/uut/PE_s(2)/S/HT_task/sram.I.data_out
-add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Ram8k8/addra
-add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Ram8k8/addrb
-add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/doutb
-add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/dina
-add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/wea(0)
-add wave -noupdate /mpi_test/uut/dyn_HT/PE_D(3)/D/HT_task/RunState
-add wave -noupdate /mpi_test/uut/dyn_HT/PE_D(4)/D/HT_task/RunState
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/GPost
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Rec_WPost
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Received_get
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/GPost_Set
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Waited_Get(0)
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/GComp
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/n
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/ex1_state
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/fifo_data_out
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/n
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_address
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_rd_grant
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_wr_grant
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dest_address
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/WBUSY
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Rec_WPost
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Received_get
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Set_Wbusy
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Waited_Get(0)
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/GPost
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/GComp
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/GPost_Set
-add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data
-add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_data_available
-add wave -noupdate /mpi_test/clk
-add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/enb
-add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/wea(0)
-add wave -noupdate -radix binary /mpi_test/uut/PE_s(2)/S/Ram8k8/doutb
-add wave -noupdate -radix binary /mpi_test/uut/PE_s(2)/S/Ram8k8/dina
-add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Ram8k8/addrb
-add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Ram8k8/addra
+add wave -noupdate /simu_tree/reset
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/fifo_wr
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/wr_en
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/nib
+add wave -noupdate /simu_tree/sw
+add wave -noupdate /simu_tree/led
+add wave -noupdate /simu_tree/uut/etsnd3
+add wave -noupdate -radix hexadecimal /simu_tree/uut/PortIn(3)
+add wave -noupdate -radix hexadecimal /simu_tree/uut/PortIn(6)
+add wave -noupdate /simu_tree/uut/etsnd2
+add wave -noupdate -radix hexadecimal /simu_tree/uut/PortIn(2)
+add wave -noupdate /simu_tree/uut/etsnd1
+add wave -noupdate -radix hexadecimal -childformat {{/simu_tree/uut/PortIn(1)(15) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(14) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(13) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(12) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(11) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(10) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(9) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(8) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(7) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(6) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(5) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(4) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(3) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(2) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(1) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(0) -radix hexadecimal}} -subitemconfig {/simu_tree/uut/PortIn(1)(15) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(14) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(13) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(12) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(11) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(10) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(9) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(8) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(7) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(6) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(5) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(4) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(3) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(2) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(1) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(0) {-height 18 -radix hexadecimal}} /simu_tree/uut/PortIn(1)
+add wave -noupdate /simu_tree/uut/etrec
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/Et_store
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/wr_en
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/data_in
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/data_out
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/nib
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/fifo_in
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/fifo_wr
+add wave -noupdate /simu_tree/uut/etcmd
+add wave -noupdate -radix hexadecimal -childformat {{/simu_tree/uut/portOut(1) -radix hexadecimal} {/simu_tree/uut/portOut(2) -radix hexadecimal} {/simu_tree/uut/portOut(3) -radix hexadecimal} {/simu_tree/uut/portOut(4) -radix hexadecimal} {/simu_tree/uut/portOut(5) -radix hexadecimal} {/simu_tree/uut/portOut(6) -radix hexadecimal} {/simu_tree/uut/portOut(7) -radix hexadecimal} {/simu_tree/uut/portOut(8) -radix hexadecimal}} -expand -subitemconfig {/simu_tree/uut/portOut(1) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(2) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(3) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(4) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(5) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(6) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(7) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(8) {-height 18 -radix hexadecimal}} /simu_tree/uut/portOut
+add wave -noupdate /simu_tree/uut/data_available
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pop_state
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/nib
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/fifo_read_signal
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/fifo_out_signal
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/fifo_out2
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/push_dout
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/data_out
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pipeline_latch
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pipeline_latch_en
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/data_out_pulse
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/cmdstate
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pop_state
+add wave -noupdate /simu_tree/clkm
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/fifo_out_signal
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/fifo_out2
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/push_dout
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/wrok
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pipeline_latch
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pipeline_latch_en
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/cmd_data_signal
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/data_out
+add wave -noupdate /simu_tree/uut/etcmd
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(3)/PORTx4_INPUT_PORT_MODULE/request_latch
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(3)/PORTx4_INPUT_PORT_MODULE/PORT_ID
+add wave -noupdate -radix hexadecimal /simu_tree/uut/PortIn(1)
+add wave -noupdate -radix hexadecimal /simu_tree/uut/portOut(1)
+add wave -noupdate /simu_tree/uut/cmd_in_en
+add wave -noupdate /simu_tree/uut/sorigport
+add wave -noupdate /simu_tree/uut/data_available
+add wave -noupdate -radix hexadecimal -childformat {{/simu_tree/uut/PortIn(1) -radix hexadecimal} {/simu_tree/uut/PortIn(2) -radix hexadecimal} {/simu_tree/uut/PortIn(3) -radix hexadecimal} {/simu_tree/uut/PortIn(4) -radix hexadecimal} {/simu_tree/uut/PortIn(5) -radix hexadecimal} {/simu_tree/uut/PortIn(6) -radix hexadecimal} {/simu_tree/uut/PortIn(7) -radix hexadecimal} {/simu_tree/uut/PortIn(8) -radix hexadecimal}} -expand -subitemconfig {/simu_tree/uut/PortIn(1) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(2) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(3) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(4) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(5) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(6) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(7) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(8) {-height 18 -radix hexadecimal}} /simu_tree/uut/PortIn
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(3)/PORTx4_INPUT_PORT_MODULE/cmdstate
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(3)/PORTx4_INPUT_PORT_MODULE/cmd_data_signal
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(3)/PORTx4_INPUT_PORT_MODULE/cmd_data_out_pulse
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/Et_store
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/wr_en
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/data_in
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/fifo_in
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/fifo_wr
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/data_avalaible
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/data_out
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pop_state
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/fifo_out_signal
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/request_latch_en
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/request_latch
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/pop_state
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/fifo_out_signal
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/request_latch_en
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/data_out_pulse
+add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/data_out
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/request
+add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/request_latch
+add wave -noupdate /simu_tree/uut/x1/noc_data_out_en(10)
+add wave -noupdate /simu_tree/uut/x1/noc_data_out_en
+add wave -noupdate /simu_tree/uut/x1/noc_data_out_en(5)
+add wave -noupdate /simu_tree/uut/x1/noc_fifo_in_full(5)
+add wave -noupdate /simu_tree/uut/x1/noc_fifo_in_full(10)
+add wave -noupdate /simu_tree/uut/x1/tree_data_available(1)
+add wave -noupdate /simu_tree/uut/x1/tree_fifo_in_full(1)
+add wave -noupdate /simu_tree/uut/x1/noc_data_available(5)
+add wave -noupdate /simu_tree/uut/x1/noc_data_in_en
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {13042 ps} 0} {{Cursor 2} {31415000 ps} 0} {{Cursor 3} {100265000 ps} 0}
+WaveRestoreCursors {{Cursor 3} {6075000 ps} 0}
 quietly wave cursor active 1
 configure wave -namecolwidth 165
@@ -144 +102 @@
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 ps} {74096 ps}
+WaveRestoreZoom {6873500 ps} {6927711 ps}