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Changeset 18 for PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_CORE_COMPONENTS.gise
- Timestamp:
- Nov 29, 2012, 6:14:01 PM (12 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
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PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_CORE_COMPONENTS.gise
r15 r18 23 23 24 24 <files xmlns="http://www.xilinx.com/XMLSchema"> 25 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="CORE_MPI.bld"/>26 <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="CORE_MPI.cmd_log"/>27 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="CORE_MPI.lso"/>28 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="CORE_MPI.ncd" xil_pn:subbranch="Par"/>29 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="CORE_MPI.ngc"/>30 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="CORE_MPI.ngd"/>31 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="CORE_MPI.ngr"/>32 <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="CORE_MPI.pad"/>33 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="CORE_MPI.par" xil_pn:subbranch="Par"/>34 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="CORE_MPI.pcf" xil_pn:subbranch="Map"/>35 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="CORE_MPI.prj"/>36 <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="CORE_MPI.ptwx"/>37 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="CORE_MPI.stx"/>38 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="CORE_MPI.syr"/>39 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="CORE_MPI.twr" xil_pn:subbranch="Par"/>40 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="CORE_MPI.twx" xil_pn:subbranch="Par"/>41 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="CORE_MPI.unroutes" xil_pn:subbranch="Par"/>42 <file xil_pn:fileType="FILE_XPI" xil_pn:name="CORE_MPI.xpi"/>43 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="CORE_MPI.xst"/>44 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="CORE_MPI_beh.prj"/>45 <file xil_pn:fileType="FILE_HTML" xil_pn:name="CORE_MPI_envsettings.html"/>46 25 <file xil_pn:fileType="FILE_NCD" xil_pn:name="CORE_MPI_guide.ncd" xil_pn:origination="imported"/> 47 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="CORE_MPI_map.map" xil_pn:subbranch="Map"/>48 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="CORE_MPI_map.mrp" xil_pn:subbranch="Map"/>49 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="CORE_MPI_map.ncd" xil_pn:subbranch="Map"/>50 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="CORE_MPI_map.ngm" xil_pn:subbranch="Map"/>51 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="CORE_MPI_map.xrpt"/>52 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="CORE_MPI_ngdbuild.xrpt"/>53 <file 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xil_pn:name="MPICORETEST.cmd_log"/>64 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="MPICORETEST.fdo"/>65 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="MPICORETEST.lso"/>66 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MPICORETEST.prj"/>67 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="MPICORETEST.syr"/>68 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="MPICORETEST.xst"/>69 28 <file xil_pn:fileType="FILE_NCD" xil_pn:name="MPICORETEST_guide.ncd" xil_pn:origination="imported"/> 70 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="MPICORETEST_isim_beh.exe"/>71 <file xil_pn:fileType="FILE_HTML" xil_pn:name="MPICORETEST_summary.html"/>72 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MPICORETEST_vhdl.prj"/>73 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MPICORETEST_xst.xrpt"/>74 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MPI_NOC.bld"/>75 <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="MPI_NOC.cmd_log"/>76 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="MPI_NOC.lso"/>77 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MPI_NOC.ncd" xil_pn:subbranch="Par"/>78 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="MPI_NOC.ngc"/>79 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="MPI_NOC.ngd"/>80 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="MPI_NOC.ngr"/>81 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="MPI_NOC.par" xil_pn:subbranch="Par"/>82 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="MPI_NOC.pcf" xil_pn:subbranch="Map"/>83 <file xil_pn:branch="Implementation" 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xil_pn:value="ReadyToRun"/> 191 </transform> 192 <transform xil_pn:end_ts="1353950850" xil_pn:in_ck="6795544366157925958" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1353950850"> 193 <status xil_pn:value="SuccessfullyRun"/> 194 <status xil_pn:value="ReadyToRun"/> 195 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/> 196 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/> 197 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbar.vhd"/> 198 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbit.vhd"/> 199 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd"/> 200 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd"/> 201 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd"/> 202 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Proto_receiv.vhd"/> 203 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/RAM_256.vhd"/> 204 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD"/> 205 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD"/> 206 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD"/> 207 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD"/> 208 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD"/> 209 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD"/> 210 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD"/> 211 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD"/> 212 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD"/> 213 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD"/> 214 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD"/> 215 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD"/> 216 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd"/> 217 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Scheduler.vhd"/> 218 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/proto_send.vhd"/> 219 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/stimuli1.vhd"/> 220 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd"/> 221 <outfile xil_pn:name="CORE_MPI.vhd"/> 222 <outfile xil_pn:name="DEMUX1.vhd"/> 223 <outfile xil_pn:name="DMA_ARBITER.vhd"/> 224 <outfile xil_pn:name="EX1_FSM.vhd"/> 225 <outfile xil_pn:name="EX2_FSM.vhd"/> 226 <outfile xil_pn:name="EX3_FSM.vhd"/> 227 <outfile xil_pn:name="EX4_FSM.vhd"/> 228 <outfile xil_pn:name="Ex0_Fsm.vhd"/> 229 <outfile xil_pn:name="FIFO_64_FWFT.vhd"/> 230 <outfile xil_pn:name="FIfo_mem.vhd"/> 231 <outfile xil_pn:name="FIfo_proc.vhd"/> 232 <outfile xil_pn:name="MPICORETEST.vhd"/> 233 <outfile xil_pn:name="MPI_CORE_SCHEDULER.vhd"/> 234 <outfile xil_pn:name="MPI_NOC.vhd"/> 235 <outfile xil_pn:name="MPI_PKG.vhd"/> 236 <outfile xil_pn:name="MPI_RMA.vhd"/> 237 <outfile xil_pn:name="MUX1.vhd"/> 238 <outfile xil_pn:name="MUX8.vhd"/> 239 <outfile xil_pn:name="MultiMPITest.vhd"/> 240 <outfile xil_pn:name="PE.vhd"/> 241 <outfile xil_pn:name="Packet_type.vhd"/> 242 <outfile xil_pn:name="RAM_32_32.vhd"/> 243 <outfile xil_pn:name="RAM_64.vhd"/> 244 <outfile xil_pn:name="load_instr.vhd"/> 245 <outfile xil_pn:name="round_robbin_machine.vhd"/> 246 <outfile xil_pn:name="sim_fifo.vhd"/> 247 </transform> 248 <transform xil_pn:end_ts="1353951434" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8804766714685316537" xil_pn:start_ts="1353951434"> 249 <status xil_pn:value="SuccessfullyRun"/> 250 <status xil_pn:value="ReadyToRun"/> 251 </transform> 252 <transform xil_pn:end_ts="1353951434" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="225563001328936133" xil_pn:start_ts="1353951434"> 253 <status xil_pn:value="SuccessfullyRun"/> 254 <status xil_pn:value="ReadyToRun"/> 255 </transform> 256 <transform xil_pn:end_ts="1352891540" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="8414388184515446556" xil_pn:start_ts="1352891540"> 257 <status xil_pn:value="SuccessfullyRun"/> 258 <status xil_pn:value="ReadyToRun"/> 259 </transform> 260 <transform xil_pn:end_ts="1353950850" xil_pn:in_ck="6795544366157925958" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1353950850"> 261 <status xil_pn:value="SuccessfullyRun"/> 262 <status xil_pn:value="ReadyToRun"/> 263 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/> 264 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/> 265 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbar.vhd"/> 266 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbit.vhd"/> 267 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd"/> 268 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd"/> 269 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd"/> 270 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Proto_receiv.vhd"/> 271 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/RAM_256.vhd"/> 272 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD"/> 273 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD"/> 274 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD"/> 275 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD"/> 276 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD"/> 277 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD"/> 278 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD"/> 279 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD"/> 280 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD"/> 281 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD"/> 282 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD"/> 283 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD"/> 284 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd"/> 285 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Scheduler.vhd"/> 286 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/proto_send.vhd"/> 287 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/stimuli1.vhd"/> 288 <outfile xil_pn:name="../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd"/> 289 <outfile xil_pn:name="CORE_MPI.vhd"/> 290 <outfile xil_pn:name="DEMUX1.vhd"/> 291 <outfile xil_pn:name="DMA_ARBITER.vhd"/> 292 <outfile xil_pn:name="EX1_FSM.vhd"/> 293 <outfile xil_pn:name="EX2_FSM.vhd"/> 294 <outfile xil_pn:name="EX3_FSM.vhd"/> 295 <outfile xil_pn:name="EX4_FSM.vhd"/> 296 <outfile xil_pn:name="Ex0_Fsm.vhd"/> 297 <outfile xil_pn:name="FIFO_64_FWFT.vhd"/> 298 <outfile xil_pn:name="FIfo_mem.vhd"/> 299 <outfile xil_pn:name="FIfo_proc.vhd"/> 300 <outfile xil_pn:name="MPICORETEST.vhd"/> 301 <outfile xil_pn:name="MPI_CORE_SCHEDULER.vhd"/> 302 <outfile xil_pn:name="MPI_NOC.vhd"/> 303 <outfile xil_pn:name="MPI_PKG.vhd"/> 304 <outfile xil_pn:name="MPI_RMA.vhd"/> 305 <outfile xil_pn:name="MUX1.vhd"/> 306 <outfile xil_pn:name="MUX8.vhd"/> 307 <outfile xil_pn:name="MultiMPITest.vhd"/> 308 <outfile xil_pn:name="PE.vhd"/> 309 <outfile xil_pn:name="Packet_type.vhd"/> 310 <outfile xil_pn:name="RAM_32_32.vhd"/> 311 <outfile xil_pn:name="RAM_64.vhd"/> 312 <outfile xil_pn:name="load_instr.vhd"/> 313 <outfile xil_pn:name="round_robbin_machine.vhd"/> 314 <outfile xil_pn:name="sim_fifo.vhd"/> 315 </transform> 316 <transform xil_pn:end_ts="1353951464" xil_pn:in_ck="6795544366157925958" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-69836859381131890" xil_pn:start_ts="1353951434"> 317 <status xil_pn:value="SuccessfullyRun"/> 318 <status xil_pn:value="ReadyToRun"/> 319 <outfile xil_pn:name="MultiMPITest_beh.prj"/> 320 <outfile xil_pn:name="MultiMPITest_isim_beh.exe"/> 321 <outfile xil_pn:name="fuse.log"/> 322 <outfile xil_pn:name="isim"/> 323 <outfile xil_pn:name="xilinxsim.ini"/> 324 </transform> 325 <transform xil_pn:end_ts="1353951464" xil_pn:in_ck="5972306979604129699" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4736240422826914561" xil_pn:start_ts="1353951464"> 326 <status xil_pn:value="SuccessfullyRun"/> 327 <status xil_pn:value="ReadyToRun"/> 328 <outfile xil_pn:name="MultiMPITest_isim_beh.wdb"/> 329 <outfile xil_pn:name="isim.cmd"/> 330 </transform> 331 <transform xil_pn:end_ts="1344237304" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1344237304"> 332 <status xil_pn:value="SuccessfullyRun"/> 333 <status xil_pn:value="ReadyToRun"/> 334 </transform> 335 <transform xil_pn:end_ts="1345373166" xil_pn:in_ck="5944890944412384878" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4542759591300251492" xil_pn:start_ts="1345373166"> 336 <status xil_pn:value="SuccessfullyRun"/> 337 <status xil_pn:value="ReadyToRun"/> 338 <status xil_pn:value="OutOfDateForInputs"/> 339 <status xil_pn:value="OutOfDateForProperties"/> 340 <status xil_pn:value="InputChanged"/> 341 </transform> 342 </transforms> 35 <transforms xmlns="http://www.xilinx.com/XMLSchema"/> 343 36 344 37 </generated_project>
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