Changeset 36 for PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES

Timestamp:

Dec 3, 2012, 2:58:14 PM (12 years ago)

Author:

rolagamo

Message:

Ceci est la version stable pour les tests

File:

• PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.01/CoreTypes.vhd (modified) (3 diffs)

PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.01/CoreTypes.vhd

@@ -7 +7 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;
-
+use IEEE.numeric_std.all;
 package CoreTypes is
 CONSTANT Word :POSITIVE:= 8;
@@ -145 +145 @@
   FUNCTION Rol_Vec(s1:std_logic_vector) return std_logic_vector;
   --renvoie un std_logic_vector de taille ADRLEN
-  Function Stdlv (s1 : natural ) return std_logic_vector;
+  Function Stdlv (s1 : natural) return std_logic_vector;
+  --renvoie un std_logic_vector de taille width
+  Function Stdlv (s1 : natural;width:positive ) return std_logic_vector;
 end CoreTypes;
 
@@ -225 +227 @@
         end Rol_vec;
  Function Stdlv (s1 : natural ) return std_logic_vector is
-VARIABLE V : std_logic_vector(ADRLEN-1 downto 0)
+VARIABLE V : std_logic_vector(ADRLEN-1 downto 0);
  begin
         V:=std_logic_vector(to_unsigned(s1,ADRLEN));
         return V;
  end stdlv;
+ Function Stdlv (s1 : natural;width:positive ) return std_logic_vector is
+VARIABLE V : std_logic_vector(width-1 downto 0);
+ begin
+        V:=std_logic_vector(to_unsigned(s1,width));
+        return V;
+ end stdlv;
 end CoreTypes;