Ignore:
Timestamp:
Dec 3, 2012, 2:58:14 PM (12 years ago)
Author:
rolagamo
Message:

Ceci est la version stable pour les tests

File:
1 edited

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  • PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.01/CoreTypes.vhd

    r22 r36  
    77library IEEE;
    88use IEEE.STD_LOGIC_1164.all;
    9 
     9use IEEE.numeric_std.all;
    1010package CoreTypes is
    1111CONSTANT Word :POSITIVE:= 8;
     
    145145  FUNCTION Rol_Vec(s1:std_logic_vector) return std_logic_vector;
    146146  --renvoie un std_logic_vector de taille ADRLEN
    147   Function Stdlv (s1 : natural ) return std_logic_vector;
     147  Function Stdlv (s1 : natural) return std_logic_vector;
     148  --renvoie un std_logic_vector de taille width
     149  Function Stdlv (s1 : natural;width:positive ) return std_logic_vector;
    148150end CoreTypes;
    149151
     
    225227        end Rol_vec;
    226228 Function Stdlv (s1 : natural ) return std_logic_vector is
    227 VARIABLE V : std_logic_vector(ADRLEN-1 downto 0)
     229VARIABLE V : std_logic_vector(ADRLEN-1 downto 0);
    228230 begin
    229231        V:=std_logic_vector(to_unsigned(s1,ADRLEN));
    230232        return V;
    231233 end stdlv;
     234 Function Stdlv (s1 : natural;width:positive ) return std_logic_vector is
     235VARIABLE V : std_logic_vector(width-1 downto 0);
     236 begin
     237        V:=std_logic_vector(to_unsigned(s1,width));
     238        return V;
     239 end stdlv;
    232240end CoreTypes;
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