Ignore:
Timestamp:
Dec 20, 2012, 3:42:20 PM (12 years ago)
Author:
rolagamo
Message:

Ceci est la version stable avant optimisation

File:
1 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_COMPONENTS.xise

    r39 r41  
    1818    <file xil_pn:name="MUX1.vhd" xil_pn:type="FILE_VHDL">
    1919      <association xil_pn:name="BehavioralSimulation"/>
    20       <association xil_pn:name="PostMapSimulation"/>
    21       <association xil_pn:name="PostRouteSimulation"/>
    22       <association xil_pn:name="PostTranslateSimulation"/>
     20      <association xil_pn:name="Implementation"/>
    2321    </file>
    2422    <file xil_pn:name="MUX8.vhd" xil_pn:type="FILE_VHDL">
    … …  
    342340    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    343341    <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    344     <property xil_pn:name="Device" xil_pn:value="xc6slx100" xil_pn:valueState="non-default"/>
     342    <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
    345343    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
    346344    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
    … …  
    493491    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
    494492    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
    495     <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
     493    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
    496494    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    497495    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    521519    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
    522520    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    523     <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
     521    <property xil_pn:name="RAM Style" xil_pn:value="Block" xil_pn:valueState="non-default"/>
    524522    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    525523    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
    … …  
    628626    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
    629627    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
    630     <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
     628    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="d:/Xilinx/12.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
    631629    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
    632630    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
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