Ignore:
Timestamp:
Dec 20, 2012, 3:42:20 PM (12 years ago)
Author:
rolagamo
Message:

Ceci est la version stable avant optimisation

Location:
PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/iseconfig
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/iseconfig/MPI_CORE_COMPONENTS.projectmgr

    r28 r41  
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  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/iseconfig/MultiMPITest.xreport

    r39 r41  
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    195    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
    196    <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/MultiMPITest_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
    197    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_sta.nlf" label="Primetime Netlist Report" >
    198     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    199    </view>
    200    <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.ibs" label="IBIS Model" >
     180   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/SWITCH_GEN_map.nlf" label="Post-Map Simulation Model Report" />
     181   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_map.psr" label="Physical Synthesis Report" >
     182    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     183   </view>
     184   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="SWITCH_GEN_pad.txt" label="Pad Report" >
     185    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     186   </view>
     187   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN.unroutes" label="Unroutes Report" >
     188    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     189   </view>
     190   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.tsi" label="Post-Map Constraints Interaction Report" >
     191    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     192   </view>
     193   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.grf" label="Guide Results Report" />
     194   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.dly" label="Asynchronous Delay Report" />
     195   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.clk_rgn" label="Clock Region Report" />
     196   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.tsi" label="Post-Place and Route Constraints Interaction Report" >
     197    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     198   </view>
     199   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
     200   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/SWITCH_GEN_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
     201   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_sta.nlf" label="Primetime Netlist Report" >
     202    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     203   </view>
     204   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.ibs" label="IBIS Model" >
    201205    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
    202206    <toc-item title="Component" target="Component " />
    203207   </view>
    204    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.lck" label="Back-annotate Pin Report" >
     208   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lck" label="Back-annotate Pin Report" >
    205209    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
    206210    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
    207211   </view>
    208    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.lpc" label="Locked Pin Constraints" >
     212   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lpc" label="Locked Pin Constraints" >
    209213    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
    210214    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
    211215   </view>
    212    <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/MultiMPITest_timesim.nlf" label="Post-Fit Simulation Model Report" />
     216   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/SWITCH_GEN_timesim.nlf" label="Post-Fit Simulation Model Report" />
    213217   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
    214218   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
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