Ignore:
Timestamp:
Apr 22, 2013, 11:35:01 AM (11 years ago)
Author:
rolagamo
Message:
 
File:
1 edited

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  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MPI_CORE_COMPONENTS.xise

    r41 r64  
    6969    </file>
    7070    <file xil_pn:name="MPI_PKG.vhd" xil_pn:type="FILE_VHDL">
    71       <association xil_pn:name="BehavioralSimulation"/>
    7271      <association xil_pn:name="Implementation"/>
    7372    </file>
    … …  
    8281    </file>
    8382    <file xil_pn:name="../SWITCH_GENERIC_16_16/conv.vhd" xil_pn:type="FILE_VHDL">
     83      <association xil_pn:name="BehavioralSimulation"/>
     84      <association xil_pn:name="Implementation"/>
    8485      <library xil_pn:name="NocLib"/>
    8586    </file>
    … …  
    125126    </file>
    126127    <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD" xil_pn:type="FILE_VHDL">
     128      <association xil_pn:name="BehavioralSimulation"/>
    127129      <association xil_pn:name="Implementation"/>
    128130      <library xil_pn:name="NocLib"/>
    129131    </file>
    130132    <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD" xil_pn:type="FILE_VHDL">
     133      <association xil_pn:name="BehavioralSimulation"/>
    131134      <association xil_pn:name="Implementation"/>
    132135      <library xil_pn:name="NocLib"/>
    … …  
    193196    </file>
    194197    <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD" xil_pn:type="FILE_VHDL">
     198      <association xil_pn:name="BehavioralSimulation"/>
    195199      <association xil_pn:name="Implementation"/>
    196200      <library xil_pn:name="NocLib"/>
    197201    </file>
    198202    <file xil_pn:name="../SWITCH_GENERIC_16_16/stimuli1.vhd" xil_pn:type="FILE_VHDL">
     203      <association xil_pn:name="BehavioralSimulation"/>
     204      <association xil_pn:name="Implementation"/>
     205      <library xil_pn:name="NocLib"/>
     206    </file>
     207    <file xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL">
     208      <association xil_pn:name="BehavioralSimulation"/>
     209      <association xil_pn:name="Implementation"/>
     210      <library xil_pn:name="NocLib"/>
     211    </file>
     212    <file xil_pn:name="../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd" xil_pn:type="FILE_VHDL">
     213      <association xil_pn:name="BehavioralSimulation"/>
     214      <association xil_pn:name="Implementation"/>
     215      <library xil_pn:name="NocLib"/>
     216    </file>
     217    <file xil_pn:name="RAM_32_32.vhd" xil_pn:type="FILE_VHDL">
     218      <association xil_pn:name="BehavioralSimulation"/>
     219      <association xil_pn:name="Implementation"/>
     220    </file>
     221    <file xil_pn:name="Ex0_Fsm.vhd" xil_pn:type="FILE_VHDL">
     222      <association xil_pn:name="BehavioralSimulation"/>
     223      <association xil_pn:name="Implementation"/>
     224    </file>
     225    <file xil_pn:name="EX4_FSM.vhd" xil_pn:type="FILE_VHDL">
     226      <association xil_pn:name="BehavioralSimulation"/>
     227      <association xil_pn:name="Implementation"/>
     228    </file>
     229    <file xil_pn:name="MPI_NOC.ucf" xil_pn:type="FILE_UCF">
     230      <association xil_pn:name="Implementation"/>
     231    </file>
     232    <file xil_pn:name="MPICORETEST.vhd" xil_pn:type="FILE_VHDL">
     233      <association xil_pn:name="BehavioralSimulation"/>
     234      <association xil_pn:name="Implementation"/>
     235    </file>
     236    <file xil_pn:name="load_instr.vhd" xil_pn:type="FILE_VHDL">
     237      <association xil_pn:name="BehavioralSimulation"/>
     238      <association xil_pn:name="Implementation"/>
     239    </file>
     240    <file xil_pn:name="PE.vhd" xil_pn:type="FILE_VHDL">
     241      <association xil_pn:name="BehavioralSimulation"/>
     242      <association xil_pn:name="Implementation"/>
     243    </file>
     244    <file xil_pn:name="MultiMPITest.vhd" xil_pn:type="FILE_VHDL">
     245      <association xil_pn:name="BehavioralSimulation"/>
     246      <association xil_pn:name="Implementation"/>
     247    </file>
     248    <file xil_pn:name="MPI_RMA.vhd" xil_pn:type="FILE_VHDL">
     249      <association xil_pn:name="BehavioralSimulation"/>
     250      <association xil_pn:name="Implementation"/>
     251    </file>
     252    <file xil_pn:name="MultiMPITest.ucf" xil_pn:type="FILE_UCF">
     253      <association xil_pn:name="Implementation"/>
     254    </file>
     255    <file xil_pn:name="FIfo_mem.vhd" xil_pn:type="FILE_VHDL">
     256      <association xil_pn:name="BehavioralSimulation"/>
     257      <association xil_pn:name="Implementation"/>
     258    </file>
     259    <file xil_pn:name="FIfo_proc.vhd" xil_pn:type="FILE_VHDL">
     260      <association xil_pn:name="BehavioralSimulation"/>
     261      <association xil_pn:name="Implementation"/>
     262    </file>
     263    <file xil_pn:name="sim_fifo.vhd" xil_pn:type="FILE_VHDL">
     264      <association xil_pn:name="BehavioralSimulation"/>
     265      <association xil_pn:name="Implementation"/>
     266    </file>
     267    <file xil_pn:name="../SWITCH_GENERIC_16_16/Proto_receiv.vhd" xil_pn:type="FILE_VHDL">
     268      <association xil_pn:name="BehavioralSimulation"/>
     269      <association xil_pn:name="Implementation"/>
     270      <library xil_pn:name="NocLib"/>
     271    </file>
     272    <file xil_pn:name="../SWITCH_GENERIC_16_16/proto_send.vhd" xil_pn:type="FILE_VHDL">
     273      <association xil_pn:name="BehavioralSimulation"/>
     274      <association xil_pn:name="Implementation"/>
     275      <library xil_pn:name="NocLib"/>
     276    </file>
     277    <file xil_pn:name="image_pkg.vhd" xil_pn:type="FILE_VHDL">
     278      <association xil_pn:name="BehavioralSimulation"/>
     279      <association xil_pn:name="Implementation"/>
     280    </file>
     281    <file xil_pn:name="SWITCH_GEN.ucf" xil_pn:type="FILE_UCF">
     282      <association xil_pn:name="Implementation"/>
     283    </file>
     284    <file xil_pn:name="test_DMA.vhd" xil_pn:type="FILE_VHDL">
    199285      <association xil_pn:name="BehavioralSimulation"/>
    200286      <association xil_pn:name="PostMapSimulation"/>
    201287      <association xil_pn:name="PostRouteSimulation"/>
    202288      <association xil_pn:name="PostTranslateSimulation"/>
    203       <library xil_pn:name="NocLib"/>
    204     </file>
    205     <file xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL">
    206       <association xil_pn:name="BehavioralSimulation"/>
    207       <association xil_pn:name="Implementation"/>
    208       <library xil_pn:name="NocLib"/>
    209     </file>
    210     <file xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GENERIQUE.vhd" xil_pn:type="FILE_VHDL">
    211       <library xil_pn:name="NocLib"/>
    212     </file>
    213     <file xil_pn:name="../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd" xil_pn:type="FILE_VHDL">
     289    </file>
     290    <file xil_pn:name="mem1.mem" xil_pn:type="FILE_MEM">
     291      <association xil_pn:name="Implementation"/>
     292    </file>
     293    <file xil_pn:name="mpi_test.vhd" xil_pn:type="FILE_VHDL">
    214294      <association xil_pn:name="BehavioralSimulation"/>
    215295      <association xil_pn:name="PostMapSimulation"/>
    216296      <association xil_pn:name="PostRouteSimulation"/>
    217297      <association xil_pn:name="PostTranslateSimulation"/>
    218       <library xil_pn:name="NocLib"/>
    219     </file>
    220     <file xil_pn:name="RAM_32_32.vhd" xil_pn:type="FILE_VHDL">
    221       <association xil_pn:name="BehavioralSimulation"/>
    222       <association xil_pn:name="Implementation"/>
    223     </file>
    224     <file xil_pn:name="Ex0_Fsm.vhd" xil_pn:type="FILE_VHDL">
    225       <association xil_pn:name="BehavioralSimulation"/>
    226       <association xil_pn:name="Implementation"/>
    227     </file>
    228     <file xil_pn:name="EX4_FSM.vhd" xil_pn:type="FILE_VHDL">
    229       <association xil_pn:name="BehavioralSimulation"/>
    230       <association xil_pn:name="Implementation"/>
    231     </file>
    232     <file xil_pn:name="MPI_NOC.ucf" xil_pn:type="FILE_UCF">
    233       <association xil_pn:name="Implementation"/>
    234     </file>
    235     <file xil_pn:name="MPICORETEST.vhd" xil_pn:type="FILE_VHDL">
    236       <association xil_pn:name="BehavioralSimulation"/>
    237       <association xil_pn:name="Implementation"/>
    238     </file>
    239     <file xil_pn:name="load_instr.vhd" xil_pn:type="FILE_VHDL">
    240       <association xil_pn:name="BehavioralSimulation"/>
    241       <association xil_pn:name="Implementation"/>
    242     </file>
    243     <file xil_pn:name="PE.vhd" xil_pn:type="FILE_VHDL">
    244       <association xil_pn:name="BehavioralSimulation"/>
    245       <association xil_pn:name="Implementation"/>
    246     </file>
    247     <file xil_pn:name="MultiMPITest.vhd" xil_pn:type="FILE_VHDL">
    248       <association xil_pn:name="BehavioralSimulation"/>
    249       <association xil_pn:name="Implementation"/>
    250     </file>
    251     <file xil_pn:name="MPI_RMA.vhd" xil_pn:type="FILE_VHDL">
    252       <association xil_pn:name="BehavioralSimulation"/>
    253       <association xil_pn:name="Implementation"/>
    254     </file>
    255     <file xil_pn:name="MultiMPITest.ucf" xil_pn:type="FILE_UCF">
    256       <association xil_pn:name="Implementation"/>
    257     </file>
    258     <file xil_pn:name="FIfo_mem.vhd" xil_pn:type="FILE_VHDL">
    259       <association xil_pn:name="BehavioralSimulation"/>
    260       <association xil_pn:name="Implementation"/>
    261     </file>
    262     <file xil_pn:name="FIfo_proc.vhd" xil_pn:type="FILE_VHDL">
    263       <association xil_pn:name="BehavioralSimulation"/>
    264       <association xil_pn:name="Implementation"/>
    265     </file>
    266     <file xil_pn:name="sim_fifo.vhd" xil_pn:type="FILE_VHDL">
    267       <association xil_pn:name="BehavioralSimulation"/>
    268       <association xil_pn:name="Implementation"/>
    269     </file>
    270     <file xil_pn:name="../SWITCH_GENERIC_16_16/Proto_receiv.vhd" xil_pn:type="FILE_VHDL">
    271       <association xil_pn:name="BehavioralSimulation"/>
    272       <association xil_pn:name="Implementation"/>
    273       <library xil_pn:name="NocLib"/>
    274     </file>
    275     <file xil_pn:name="../SWITCH_GENERIC_16_16/proto_send.vhd" xil_pn:type="FILE_VHDL">
    276       <association xil_pn:name="BehavioralSimulation"/>
    277       <association xil_pn:name="Implementation"/>
    278       <library xil_pn:name="NocLib"/>
    279     </file>
    280     <file xil_pn:name="image_pkg.vhd" xil_pn:type="FILE_VHDL">
     298    </file>
     299    <file xil_pn:name="MPI_HCL_Archi.sch" xil_pn:type="FILE_SCHEMATIC">
     300      <association xil_pn:name="BehavioralSimulation"/>
     301      <association xil_pn:name="Implementation"/>
     302    </file>
     303    <file xil_pn:name="Hold_FSM.vhd" xil_pn:type="FILE_VHDL">
    281304      <association xil_pn:name="BehavioralSimulation"/>
    282305      <association xil_pn:name="Implementation"/>
    … …  
    404427    <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    405428    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
    406     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     429    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
    407430    <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
    408431    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    443466    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
    444467    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
    445     <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    446     <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     468    <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
     469    <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
    447470    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    448471    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    … …  
    555578    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    556579    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
    557     <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/MultiMPITest" xil_pn:valueState="non-default"/>
    558     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.MultiMPITest" xil_pn:valueState="non-default"/>
    559     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    560     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    561     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="NocLib.stimuli45" xil_pn:valueState="non-default"/>
    562     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
     580    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/mpi_test" xil_pn:valueState="non-default"/>
     581    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.mpi_test" xil_pn:valueState="non-default"/>
     582    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="NocLib.stimuli45" xil_pn:valueState="non-default"/>
     583    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="NocLib.test_xbar_8x8" xil_pn:valueState="non-default"/>
     584    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.MultiMPITest" xil_pn:valueState="non-default"/>
     585    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut" xil_pn:valueState="non-default"/>
    563586    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    564587    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    … …  
    580603    <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
    581604    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
    582     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.MultiMPITest" xil_pn:valueState="default"/>
    583     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
    584     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
    585     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="NocLib.stimuli45" xil_pn:valueState="default"/>
     605    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.mpi_test" xil_pn:valueState="default"/>
     606    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="NocLib.stimuli45" xil_pn:valueState="default"/>
     607    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="NocLib.test_xbar_8x8" xil_pn:valueState="default"/>
     608    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.MultiMPITest" xil_pn:valueState="default"/>
    586609    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
    587610    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
    … …  
    646669    <!-- The following properties are for internal use only. These should not be modified.-->
    647670    <!--                                                                                  -->
    648     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|MultiMPITest|behavior" xil_pn:valueState="non-default"/>
     671    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|mpi_test|behavior" xil_pn:valueState="non-default"/>
    649672    <property xil_pn:name="PROP_DesignName" xil_pn:value="MPI_CORE_COMPONENTS" xil_pn:valueState="non-default"/>
    650673    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
    … …  
    653676    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    654677    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    655     <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     678    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Architecture|MultiMPITest|behavior" xil_pn:valueState="non-default"/>
    656679    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
    657680    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-07-02T09:03:34" xil_pn:valueState="non-default"/>
    … …  
    664687    <binding xil_pn:location="/MPICORETEST" xil_pn:name="MPI_NOC.ucf"/>
    665688    <binding xil_pn:location="/MultiMPITest" xil_pn:name="MultiMPITest.ucf"/>
     689    <binding xil_pn:location="/SWITCH_GEN" xil_pn:name="SWITCH_GEN.ucf"/>
     690    <binding xil_pn:location="/MultiMPITest" xil_pn:name="mem1.mem"/>
    666691  </bindings>
    667692
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