Changeset 64 for PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MultiMPITest.vhd

Timestamp:

Apr 22, 2013, 11:35:01 AM (11 years ago)

Author:

rolagamo

Message:

 

File:

• PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MultiMPITest.vhd (modified) (5 diffs)

PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MultiMPITest.vhd

@@ -70 +70 @@
  
         constant clk_period : time := 10 ns;
-   constant PROC : positive :=8;
+   constant PROC : positive :=16;
 -- synthesis translate_off
 --===================signaux pour l'horloge ==============================
-signal reset,clkm : std_logic := '0';
+--signal reset,clkm : std_logic := '0';
 --========================================================================
 -- synthesis translate_on
@@ -95 +95 @@
         );
 
-PE1: PE generic map (DestId=>1)
+PE1: PE generic map (DestId=>0)
 Port Map (
 Instruction => MPi_Node_in(1).Instruction,
@@ -113 +113 @@
 );
 
-PE2: PE         Generic map (DestId=>0)
+PE2: PE         Generic map (DestId=>1)
                         Port Map (
                                 Instruction => MPi_Node_in(2).Instruction,
@@ -148 +148 @@
 );
 
---PE4: PE       Generic map (DestId=>3)
---                      Port Map (
---                              Instruction => MPi_Node_in(4).Instruction,
---           Instruction_en => MPi_Node_in(4).Instruction_en,
---                        Core_PushOut => MPi_Node_out(4).PushOut,
---           clk =>clkm,
---           reset =>reset,
---           Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out,
---           Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in,
---           Core_RAM_WE => MPI_Node_out(4).ram_we,
---           Core_RAM_EN => MPI_Node_out(4).ram_en,
---           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
---           Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr,
---           Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd,
---           Core_Hold_req => MPI_Node_out(4).hold_req,
---           Core_Hold_Ack => MPI_Node_in(4).hold_ack
---);
+PE4: PE         Generic map (DestId=>3)
+                        Port Map (
+                                Instruction => MPi_Node_in(4).Instruction,
+           Instruction_en => MPi_Node_in(4).Instruction_en,
+                          Core_PushOut => MPi_Node_out(4).PushOut,
+           clk =>clkm,
+           reset =>reset,
+           Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out,
+           Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in,
+           Core_RAM_WE => MPI_Node_out(4).ram_we,
+           Core_RAM_EN => MPI_Node_out(4).ram_en,
+           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
+           Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr,
+           Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd,
+           Core_Hold_req => MPI_Node_out(4).hold_req,
+           Core_Hold_Ack => MPI_Node_in(4).hold_ack
+);
 MPI_Node_in(1).reset<=reset;    
 MPI_Node_in(1).clk<=clkm;
@@ -178 +178 @@
 --=============================================================
 -- synthesis translate_off 
- clk_process :process
-   begin
-                clkm <= '0' ;
-                wait for clk_period/2;
-                clkm <= '1' ;
-                wait for clk_period/2;
-   end process;
- stim_proc: process 
-   begin                
+-- clk_process :process
+--   begin
+--              clkm <= '0' ;
+--              wait for clk_period/2;
+--              clkm <= '1' ;
+--              wait for clk_period/2;
+--   end process;
+-- stim_proc: process 
+--   begin              
       -- hold reset state for 100 ns.
-      reset<='0';
-                wait for 1 ns;  
-                reset<='1';
-      wait for clk_period*10;
-                reset<='0';
-                wait;
-     
-        
-        end process;
+--      reset<='0';
+--              wait for 1 ns;  
+--              reset<='1';
+--      wait for clk_period*10;
+--              reset<='0';
+--              wait;
+--     
+--      
+--      end process;
 -- synthesis translate_on
 --================================================================