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Changeset 64 for PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/iseconfig
- Timestamp:
- Apr 22, 2013, 11:35:01 AM (11 years ago)
- Location:
- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/iseconfig
- Files:
-
- 2 edited
-
MPI_CORE_COMPONENTS.projectmgr (modified) (13 diffs)
-
MultiMPITest.xreport (modified) (13 diffs)
Legend:
- Unmodified
- Added
- Removed
-
PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/iseconfig/MPI_CORE_COMPONENTS.projectmgr
r43 r64 14 14 <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/Inst_RAM_v - RAM_v - Behavioral/MPI_PKG/mpi_pkg</ClosedNode> 15 15 <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/MPI_PKG</ClosedNode> 16 <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural </ClosedNode>16 <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/CORE_SCHEDULER - MPI_CORE_SCHEDULER - Behavioral</ClosedNode> 17 17 <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo1 - FIFO_64_FWFT - Behavioral</ClosedNode> 18 18 <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo2 - FIFO_64_FWFT - Behavioral</ClosedNode> … … 184 184 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/MPI_PKG</ClosedNode> 185 185 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/PE1 - PE - Behavioral</ClosedNode> 186 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural</ClosedNode> 186 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/PE2 - PE - Behavioral</ClosedNode> 187 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/PE3 - PE - Behavioral</ClosedNode> 187 188 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/CORE_SCHEDULER - MPI_CORE_SCHEDULER - Behavioral</ClosedNode> 188 189 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral</ClosedNode> 189 <ClosedNode>/Unassigned User Library Modules</ClosedNode> 190 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 191 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 192 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 193 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 194 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT14_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 195 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT15_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 196 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT1_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 197 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 198 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT2_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 199 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT2_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 200 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT3_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 201 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT3_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 202 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT4_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 203 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT5_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 204 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT6_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 205 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT7_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 206 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT8_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 207 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT9_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 208 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx16_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 209 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx16_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 210 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 211 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 212 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 213 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler10_10 - Scheduler - Behavioral</ClosedNode> 214 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler11_11 - Scheduler - Behavioral</ClosedNode> 215 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler12_12 - Scheduler - Behavioral</ClosedNode> 216 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler13_13 - Scheduler - Behavioral</ClosedNode> 217 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler14_14 - Scheduler - Behavioral</ClosedNode> 218 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler15_15 - Scheduler - Behavioral</ClosedNode> 219 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral</ClosedNode> 220 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler2_2 - Scheduler - Behavioral</ClosedNode> 221 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler3_3 - Scheduler - Behavioral</ClosedNode> 222 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler4_4 - Scheduler - Behavioral</ClosedNode> 223 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler5_5 - Scheduler - Behavioral</ClosedNode> 224 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler6_6 - Scheduler - Behavioral</ClosedNode> 225 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler7_7 - Scheduler - Behavioral</ClosedNode> 226 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral</ClosedNode> 227 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler9_9 - Scheduler - Behavioral</ClosedNode> 228 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar10_10 - Crossbar - Behavioral</ClosedNode> 229 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar11_11 - Crossbar - Behavioral</ClosedNode> 230 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar12_12 - Crossbar - Behavioral</ClosedNode> 231 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar13_13 - Crossbar - Behavioral</ClosedNode> 232 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar14_14 - Crossbar - Behavioral</ClosedNode> 233 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar15_15 - Crossbar - Behavioral</ClosedNode> 234 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar16_16 - Crossbar - Behavioral</ClosedNode> 235 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar2_2 - Crossbar - Behavioral</ClosedNode> 236 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar3_3 - Crossbar - Behavioral</ClosedNode> 237 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar4_4 - Crossbar - Behavioral</ClosedNode> 238 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar5_5 - Crossbar - Behavioral</ClosedNode> 239 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar6_6 - Crossbar - Behavioral</ClosedNode> 240 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar7_7 - Crossbar - Behavioral</ClosedNode> 241 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar8_8 - Crossbar - Behavioral</ClosedNode> 242 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral</ClosedNode> 243 <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/conversions</ClosedNode> 244 <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd</ClosedNode> 245 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral</ClosedNode> 246 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 247 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 248 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT11_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 249 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 250 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT12_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 251 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 252 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT13_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 253 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 254 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT14_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 255 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT14_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 256 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT15_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 257 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT15_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 258 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT16_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 259 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT16_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 260 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT1_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 261 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 262 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT2_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 263 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT2_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 264 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT3_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 265 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT3_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 266 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 267 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT4_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 268 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT5_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 269 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT5_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 270 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT6_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 271 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT6_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 272 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT7_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 273 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT7_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 274 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 275 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT8_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 276 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 277 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT9_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> 278 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler10_10 - Scheduler - Behavioral</ClosedNode> 279 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler11_11 - Scheduler - Behavioral</ClosedNode> 280 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler12_12 - Scheduler - Behavioral</ClosedNode> 281 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler13_13 - Scheduler - Behavioral</ClosedNode> 282 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler14_14 - Scheduler - Behavioral</ClosedNode> 283 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler15_15 - Scheduler - Behavioral</ClosedNode> 284 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler16_16 - Scheduler - Behavioral</ClosedNode> 285 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler2_2 - Scheduler - Behavioral</ClosedNode> 286 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler3_3 - Scheduler - Behavioral</ClosedNode> 287 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler4_4 - Scheduler - Behavioral</ClosedNode> 288 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler5_5 - Scheduler - Behavioral</ClosedNode> 289 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler6_6 - Scheduler - Behavioral</ClosedNode> 290 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler7_7 - Scheduler - Behavioral</ClosedNode> 291 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler8_8 - Scheduler - Behavioral</ClosedNode> 292 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler9_9 - Scheduler - Behavioral</ClosedNode> 293 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar10_10 - Crossbar - Behavioral</ClosedNode> 294 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar11_11 - Crossbar - Behavioral</ClosedNode> 295 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar12_12 - Crossbar - Behavioral</ClosedNode> 296 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar13_13 - Crossbar - Behavioral</ClosedNode> 297 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar14_14 - Crossbar - Behavioral</ClosedNode> 298 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar15_15 - Crossbar - Behavioral</ClosedNode> 299 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar16_16 - Crossbar - Behavioral</ClosedNode> 300 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar2_2 - Crossbar - Behavioral</ClosedNode> 301 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar3_3 - Crossbar - Behavioral</ClosedNode> 302 <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar4_4 - Crossbar - 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PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/iseconfig/MultiMPITest.xreport
r41 r64 2 2 <report-views version="2.0" > 3 3 <header> 4 <DateModified>201 2-12-20T15:14:17</DateModified>5 <ModuleName> SWITCH_GEN</ModuleName>6 <SummaryTimeStamp>201 2-12-19T17:00:46</SummaryTimeStamp>4 <DateModified>2013-04-22T08:02:07</DateModified> 5 <ModuleName>DMA_ARBITER</ModuleName> 6 <SummaryTimeStamp>2013-04-10T14:49:35</SummaryTimeStamp> 7 7 <SavedFilePath>C:/Core MPI/CORE_MPI/iseconfig/MultiMPITest.xreport</SavedFilePath> 8 8 <ImplementationReportsDirectory>C:/Core MPI/CORE_MPI\</ImplementationReportsDirectory> 9 <DateInitialized>201 2-12-09T12:18:32</DateInitialized>9 <DateInitialized>2013-03-19T19:44:50</DateInitialized> 10 10 <EnableMessageFiltering>false</EnableMessageFiltering> 11 11 </header> 12 12 <body> 13 13 <viewgroup label="Design Overview" > 14 <view inputState="Unknown" program="implementation" ShowPartitionData="false" ExpandConstraints="true" type="FPGASummary" file=" SWITCH_GEN_summary.html" label="Summary" ExpandClockNets="true" ExpandWarnings="true" >14 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label="Static Timing" /> 35 <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="DMA_ARBITER_html/fit/report.htm" label="CPLD Fitter Report" /> 36 <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="DMA_ARBITER_html/tim/report.htm" label="CPLD Timing Report" /> 35 37 </viewgroup> 36 38 <viewgroup label="XPS Errors and Warnings" > … … 45 47 <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> 46 48 <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> 47 <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file=" SWITCH_GEN.log" label="System Log File" />49 <view inputState="PreSynthesized" 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contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file=" SWITCH_GEN.prec_log" label="Precision Report" />91 <view inputState="Synthesized" program="ngdbuild" type="Report" file=" SWITCH_GEN.bld" label="Translation Report" >91 <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="DMA_ARBITER.srr" label="Synplify Report" /> 92 <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="DMA_ARBITER.prec_log" label="Precision Report" /> 93 <view inputState="Synthesized" program="ngdbuild" type="Report" file="DMA_ARBITER.bld" label="Translation Report" > 92 94 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 93 95 <toc-item title="Command Line" target="Command Line:" /> … … 95 97 <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> 96 98 </view> 97 <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file=" SWITCH_GEN_map.mrp" label="Map Report" >99 <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="DMA_ARBITER_map.mrp" label="Map Report" > 98 100 <toc-item title="Top of Report" target="Release" searchDir="Forward" /> 99 101 <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> … … 111 113 <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> 112 114 </view> 113 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file=" SWITCH_GEN.par" label="Place and Route Report" >115 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="DMA_ARBITER.par" label="Place and Route Report" > 114 116 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 115 117 <toc-item title="Device Utilization" target="Device Utilization Summary:" /> … … 120 122 <toc-item title="Final Summary" target="Peak Memory Usage:" /> 121 123 </view> 122 <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file=" SWITCH_GEN.twr" label="Post-PAR Static Timing Report" >124 <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="DMA_ARBITER.twr" label="Post-PAR Static Timing Report" > 123 125 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 124 126 <toc-item title="Timing Report Description" target="Device,package,speed:" /> … … 131 133 <toc-item title="Trace Settings" target="Trace Settings:" /> 132 134 </view> 133 <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file=" SWITCH_GEN.rpt" label="CPLD Fitter Report (Text)" >135 <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="DMA_ARBITER.rpt" label="CPLD Fitter Report (Text)" > 134 136 <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> 135 137 <toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> … … 137 139 <toc-item title="Global Resources" target="** Global Control Resources **" /> 138 140 </view> 139 <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file=" SWITCH_GEN.tim" label="CPLD Timing Report (Text)" >141 <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="DMA_ARBITER.tim" label="CPLD Timing Report (Text)" > 140 142 <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> 141 143 <toc-item title="Performance Summary" target="Performance Summary:" /> 142 144 </view> 143 <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file=" SWITCH_GEN.pwr" label="Power Report" >145 <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="DMA_ARBITER.pwr" label="Power Report" > 144 146 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 145 147 <toc-item title="Power summary" target="Power summary" /> 146 148 <toc-item title="Thermal summary" target="Thermal summary" /> 147 149 </view> 148 <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file=" SWITCH_GEN.bgn" label="Bitgen Report" >150 <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="DMA_ARBITER.bgn" label="Bitgen Report" > 149 151 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 150 152 <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> … … 154 156 <viewgroup label="Secondary Reports" > 155 157 <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> 156 <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/ SWITCH_GEN_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >157 <toc-item title="Top of Report" target="Release" searchDir="Forward" /> 158 </view> 159 <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/ SWITCH_GEN_translate.nlf" label="Post-Translate Simulation Model Report" >160 <toc-item title="Top of Report" target="Release" searchDir="Forward" /> 161 </view> 162 <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file=" SWITCH_GEN_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />163 <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file=" SWITCH_GEN_map.map" label="Map Log File" >158 <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/DMA_ARBITER_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > 159 <toc-item title="Top of Report" target="Release" searchDir="Forward" /> 160 </view> 161 <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/DMA_ARBITER_translate.nlf" label="Post-Translate Simulation Model Report" > 162 <toc-item title="Top of Report" target="Release" searchDir="Forward" /> 163 </view> 164 <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> 165 <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="DMA_ARBITER_map.map" label="Map Log File" > 164 166 <toc-item title="Top of Report" target="Release" searchDir="Forward" /> 165 167 <toc-item title="Design Information" target="Design Information" /> … … 167 169 </view> 168 170 <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> 169 <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file=" SWITCH_GEN_preroute.twr" label="Post-Map Static Timing Report" >171 <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_preroute.twr" label="Post-Map Static Timing Report" > 170 172 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 171 173 <toc-item title="Timing Report Description" target="Device,package,speed:" /> … … 178 180 <toc-item title="Trace Settings" target="Trace Settings:" /> 179 181 </view> 180 <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/ SWITCH_GEN_map.nlf" label="Post-Map Simulation Model Report" />181 <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file=" SWITCH_GEN_map.psr" label="Physical Synthesis Report" >182 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 183 </view> 184 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file=" SWITCH_GEN_pad.txt" label="Pad Report" >185 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 186 </view> 187 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file=" SWITCH_GEN.unroutes" label="Unroutes Report" >188 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 189 </view> 190 <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file=" SWITCH_GEN_preroute.tsi" label="Post-Map Constraints Interaction Report" >191 <toc-item title="Top of Report" target="Release" searchDir="Forward" /> 192 </view> 193 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file=" SWITCH_GEN.grf" label="Guide Results Report" />194 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file=" SWITCH_GEN.dly" label="Asynchronous Delay Report" />195 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file=" SWITCH_GEN.clk_rgn" label="Clock Region Report" />196 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file=" SWITCH_GEN.tsi" label="Post-Place and Route Constraints Interaction Report" >197 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 198 </view> 199 <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file=" SWITCH_GEN_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />200 <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/ SWITCH_GEN_timesim.nlf" label="Post-Place and Route Simulation Model Report" />201 <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file=" SWITCH_GEN_sta.nlf" label="Primetime Netlist Report" >202 <toc-item title="Top of Report" target="Release" searchDir="Forward" /> 203 </view> 204 <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file=" SWITCH_GEN.ibs" label="IBIS Model" >182 <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/DMA_ARBITER_map.nlf" label="Post-Map Simulation Model Report" /> 183 <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_map.psr" label="Physical Synthesis Report" > 184 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 185 </view> 186 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="DMA_ARBITER_pad.txt" label="Pad Report" > 187 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 188 </view> 189 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="DMA_ARBITER.unroutes" label="Unroutes Report" > 190 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 191 </view> 192 <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_preroute.tsi" label="Post-Map Constraints Interaction Report" > 193 <toc-item title="Top of Report" target="Release" searchDir="Forward" /> 194 </view> 195 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.grf" label="Guide Results Report" /> 196 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.dly" label="Asynchronous Delay Report" /> 197 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.clk_rgn" label="Clock Region Report" /> 198 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.tsi" label="Post-Place and Route Constraints Interaction Report" > 199 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> 200 </view> 201 <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> 202 <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/DMA_ARBITER_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> 203 <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_sta.nlf" label="Primetime Netlist Report" > 204 <toc-item title="Top of Report" target="Release" searchDir="Forward" /> 205 </view> 206 <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.ibs" label="IBIS Model" > 205 207 <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> 206 208 <toc-item title="Component" target="Component " /> 207 209 </view> 208 <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file=" SWITCH_GEN.lck" label="Back-annotate Pin Report" >210 <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.lck" label="Back-annotate Pin Report" > 209 211 <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> 210 212 <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> 211 213 </view> 212 <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file=" SWITCH_GEN.lpc" label="Locked Pin Constraints" >214 <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.lpc" label="Locked Pin Constraints" > 213 215 <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> 214 216 <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> 215 217 </view> 216 <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/ SWITCH_GEN_timesim.nlf" label="Post-Fit Simulation Model Report" />218 <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/DMA_ARBITER_timesim.nlf" label="Post-Fit Simulation Model Report" /> 217 219 <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> 218 220 <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
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