Ignore:
Timestamp:
Apr 22, 2013, 11:35:01 AM (11 years ago)
Author:
rolagamo
Message:
 
File:
1 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/iseconfig/MultiMPITest.xreport

    r41 r64  
    22<report-views version="2.0" >
    33 <header>
    4   <DateModified>2012-12-20T15:14:17</DateModified>
    5   <ModuleName>SWITCH_GEN</ModuleName>
    6   <SummaryTimeStamp>2012-12-19T17:00:46</SummaryTimeStamp>
     4  <DateModified>2013-04-22T08:02:07</DateModified>
     5  <ModuleName>DMA_ARBITER</ModuleName>
     6  <SummaryTimeStamp>2013-04-10T14:49:35</SummaryTimeStamp>
    77  <SavedFilePath>C:/Core MPI/CORE_MPI/iseconfig/MultiMPITest.xreport</SavedFilePath>
    88  <ImplementationReportsDirectory>C:/Core MPI/CORE_MPI\</ImplementationReportsDirectory>
    9   <DateInitialized>2012-12-09T12:18:32</DateInitialized>
     9  <DateInitialized>2013-03-19T19:44:50</DateInitialized>
    1010  <EnableMessageFiltering>false</EnableMessageFiltering>
    1111 </header>
    1212 <body>
    1313  <viewgroup label="Design Overview" >
    14    <view inputState="Unknown" program="implementation" ShowPartitionData="false" ExpandConstraints="true" type="FPGASummary" file="SWITCH_GEN_summary.html" label="Summary" ExpandClockNets="true" ExpandWarnings="true" >
     14   <view inputState="Unknown" program="implementation" ShowPartitionData="false" ExpandConstraints="true" type="FPGASummary" file="DMA_ARBITER_summary.html" label="Summary" ExpandClockNets="true" ExpandWarnings="true" >
    1515    <toc-item title="Design Overview" target="Design Overview" />
    1616    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
    … …  
    2222    <table-item tableState="ExpandedTable" tableKey="DeviceUtilizationSummary" />
    2323    <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" />
    24    </view>
    25    <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="SWITCH_GEN_envsettings.html" label="System Settings" />
    26    <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="SWITCH_GEN_map.xrpt" showConstraints="0" label="IOB Properties" />
    27    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="SWITCH_GEN_map.xrpt" label="Control Set Information" />
    28    <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="SWITCH_GEN_map.xrpt" label="Module Level Utilization" />
    29    <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="SWITCH_GEN.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
    30    <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="SWITCH_GEN_par.xrpt" showConstraints="0" label="Pinout Report" />
    31    <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="SWITCH_GEN_par.xrpt" showConstraints="0" label="Clock Report" />
    32    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="SWITCH_GEN.twx" label="Static Timing" />
    33    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/fit/report.htm" label="CPLD Fitter Report" />
    34    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/tim/report.htm" label="CPLD Timing Report" />
     24    <table-item tableState="CollapsedTable" tableKey="SecondaryReports" />
     25    <table-item tableState="CollapsedTable" tableKey="DetailedReports" />
     26   </view>
     27   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="DMA_ARBITER_envsettings.html" label="System Settings" />
     28   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="DMA_ARBITER_map.xrpt" showConstraints="0" label="IOB Properties" />
     29   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="DMA_ARBITER_map.xrpt" label="Control Set Information" />
     30   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="DMA_ARBITER_map.xrpt" label="Module Level Utilization" />
     31   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="DMA_ARBITER.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
     32   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="DMA_ARBITER_par.xrpt" showConstraints="0" label="Pinout Report" />
     33   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="DMA_ARBITER_par.xrpt" showConstraints="0" label="Clock Report" />
     34   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="DMA_ARBITER.twx" label="Static Timing" />
     35   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="DMA_ARBITER_html/fit/report.htm" label="CPLD Fitter Report" />
     36   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="DMA_ARBITER_html/tim/report.htm" label="CPLD Timing Report" />
    3537  </viewgroup>
    3638  <viewgroup label="XPS Errors and Warnings" >
    … …  
    4547   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
    4648   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
    47    <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="SWITCH_GEN.log" label="System Log File" />
     49   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="DMA_ARBITER.log" label="System Log File" />
    4850  </viewgroup>
    4951  <viewgroup label="Errors and Warnings" >
    … …  
    6163  </viewgroup>
    6264  <viewgroup label="Detailed Reports" >
    63    <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="SWITCH_GEN.syr" label="Synthesis Report" >
     65   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="DMA_ARBITER.syr" label="Synthesis Report" >
    6466    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
    6567    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
    … …  
    8789    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
    8890   </view>
    89    <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.srr" label="Synplify Report" />
    90    <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.prec_log" label="Precision Report" />
    91    <view inputState="Synthesized" program="ngdbuild" type="Report" file="SWITCH_GEN.bld" label="Translation Report" >
     91   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="DMA_ARBITER.srr" label="Synplify Report" />
     92   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="DMA_ARBITER.prec_log" label="Precision Report" />
     93   <view inputState="Synthesized" program="ngdbuild" type="Report" file="DMA_ARBITER.bld" label="Translation Report" >
    9294    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    9395    <toc-item title="Command Line" target="Command Line:" />
    … …  
    9597    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
    9698   </view>
    97    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN_map.mrp" label="Map Report" >
     99   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="DMA_ARBITER_map.mrp" label="Map Report" >
    98100    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    99101    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
    … …  
    111113    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
    112114   </view>
    113    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.par" label="Place and Route Report" >
     115   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="DMA_ARBITER.par" label="Place and Route Report" >
    114116    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    115117    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
    … …  
    120122    <toc-item title="Final Summary" target="Peak Memory Usage:" />
    121123   </view>
    122    <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.twr" label="Post-PAR Static Timing Report" >
     124   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="DMA_ARBITER.twr" label="Post-PAR Static Timing Report" >
    123125    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    124126    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    … …  
    131133    <toc-item title="Trace Settings" target="Trace Settings:" />
    132134   </view>
    133    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.rpt" label="CPLD Fitter Report (Text)" >
     135   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="DMA_ARBITER.rpt" label="CPLD Fitter Report (Text)" >
    134136    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
    135137    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
    … …  
    137139    <toc-item title="Global Resources" target="** Global Control Resources **" />
    138140   </view>
    139    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.tim" label="CPLD Timing Report (Text)" >
     141   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="DMA_ARBITER.tim" label="CPLD Timing Report (Text)" >
    140142    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
    141143    <toc-item title="Performance Summary" target="Performance Summary:" />
    142144   </view>
    143    <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="SWITCH_GEN.pwr" label="Power Report" >
     145   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="DMA_ARBITER.pwr" label="Power Report" >
    144146    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    145147    <toc-item title="Power summary" target="Power summary" />
    146148    <toc-item title="Thermal summary" target="Thermal summary" />
    147149   </view>
    148    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.bgn" label="Bitgen Report" >
     150   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="DMA_ARBITER.bgn" label="Bitgen Report" >
    149151    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    150152    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
    … …  
    154156  <viewgroup label="Secondary Reports" >
    155157   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
    156    <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/SWITCH_GEN_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
    157     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    158    </view>
    159    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/SWITCH_GEN_translate.nlf" label="Post-Translate Simulation Model Report" >
    160     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    161    </view>
    162    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
    163    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN_map.map" label="Map Log File" >
     158   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/DMA_ARBITER_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
     159    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     160   </view>
     161   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/DMA_ARBITER_translate.nlf" label="Post-Translate Simulation Model Report" >
     162    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     163   </view>
     164   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
     165   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="DMA_ARBITER_map.map" label="Map Log File" >
    164166    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    165167    <toc-item title="Design Information" target="Design Information" />
    … …  
    167169   </view>
    168170   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
    169    <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.twr" label="Post-Map Static Timing Report" >
     171   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_preroute.twr" label="Post-Map Static Timing Report" >
    170172    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    171173    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    … …  
    178180    <toc-item title="Trace Settings" target="Trace Settings:" />
    179181   </view>
    180    <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/SWITCH_GEN_map.nlf" label="Post-Map Simulation Model Report" />
    181    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_map.psr" label="Physical Synthesis Report" >
    182     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    183    </view>
    184    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="SWITCH_GEN_pad.txt" label="Pad Report" >
    185     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    186    </view>
    187    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN.unroutes" label="Unroutes Report" >
    188     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    189    </view>
    190    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.tsi" label="Post-Map Constraints Interaction Report" >
    191     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    192    </view>
    193    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.grf" label="Guide Results Report" />
    194    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.dly" label="Asynchronous Delay Report" />
    195    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.clk_rgn" label="Clock Region Report" />
    196    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.tsi" label="Post-Place and Route Constraints Interaction Report" >
    197     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    198    </view>
    199    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
    200    <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/SWITCH_GEN_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
    201    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_sta.nlf" label="Primetime Netlist Report" >
    202     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    203    </view>
    204    <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.ibs" label="IBIS Model" >
     182   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/DMA_ARBITER_map.nlf" label="Post-Map Simulation Model Report" />
     183   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_map.psr" label="Physical Synthesis Report" >
     184    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     185   </view>
     186   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="DMA_ARBITER_pad.txt" label="Pad Report" >
     187    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     188   </view>
     189   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="DMA_ARBITER.unroutes" label="Unroutes Report" >
     190    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     191   </view>
     192   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_preroute.tsi" label="Post-Map Constraints Interaction Report" >
     193    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     194   </view>
     195   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.grf" label="Guide Results Report" />
     196   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.dly" label="Asynchronous Delay Report" />
     197   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.clk_rgn" label="Clock Region Report" />
     198   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.tsi" label="Post-Place and Route Constraints Interaction Report" >
     199    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     200   </view>
     201   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
     202   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/DMA_ARBITER_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
     203   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_sta.nlf" label="Primetime Netlist Report" >
     204    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     205   </view>
     206   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.ibs" label="IBIS Model" >
    205207    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
    206208    <toc-item title="Component" target="Component " />
    207209   </view>
    208    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lck" label="Back-annotate Pin Report" >
     210   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.lck" label="Back-annotate Pin Report" >
    209211    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
    210212    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
    211213   </view>
    212    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lpc" label="Locked Pin Constraints" >
     214   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.lpc" label="Locked Pin Constraints" >
    213215    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
    214216    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
    215217   </view>
    216    <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/SWITCH_GEN_timesim.nlf" label="Post-Fit Simulation Model Report" />
     218   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/DMA_ARBITER_timesim.nlf" label="Post-Fit Simulation Model Report" />
    217219   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
    218220   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
Note: See TracChangeset for help on using the changeset viewer.