Ignore:
Timestamp:
Apr 22, 2013, 11:35:33 AM (11 years ago)
Author:
rolagamo
Message:
 
File:
1 edited

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  • PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SWITCH_GEN.vhd

    r45 r65  
    3232entity SWITCH_GEN is
    3333 --type portio is array(positive range) of std_logic_vector (7 downto 0);   
    34  generic(number_of_ports : positive := 4);
     34 generic(number_of_ports : positive := 8);
    3535     port(
    3636                -- ports d'entree
    3737           Port_in : in typ_portIO(1 to number_of_ports) ;
    38 --                        Port1_in : in  STD_LOGIC_VECTOR  (7 downto 0);
    39 --           Port2_in : in  STD_LOGIC_VECTOR  (7 downto 0);
    40 --           Port3_in : in  STD_LOGIC_VECTOR  (7 downto 0);
    41 --           Port4_in : in  STD_LOGIC_VECTOR  (7 downto 0);
    42 --                        Port5_in : in  STD_LOGIC_VECTOR  (7 downto 0);
    43 --           Port6_in : in  STD_LOGIC_VECTOR  (7 downto 0);
    44 --           Port7_in : in  STD_LOGIC_VECTOR  (7 downto 0);
    45 --           Port8_in : in  STD_LOGIC_VECTOR  (7 downto 0);
    46 --                        Port9_in : in  STD_LOGIC_VECTOR  (7 downto 0);
    47 --           Port10_in : in  STD_LOGIC_VECTOR (7 downto 0);
    48 --           Port11_in : in  STD_LOGIC_VECTOR (7 downto 0);
    49 --           Port12_in : in  STD_LOGIC_VECTOR (7 downto 0);
    50 --                        Port13_in : in  STD_LOGIC_VECTOR (7 downto 0);
    51 --           Port14_in : in  STD_LOGIC_VECTOR (7 downto 0);
    52 --           Port15_in : in  STD_LOGIC_VECTOR (7 downto 0);
    53 --           Port16_in : in  STD_LOGIC_VECTOR (7 downto 0);
     38
    5439                         
    5540                          -- port de sortie
    5641                          Port_out : out  typ_portIO(1 to number_of_ports);
    57 --                        Port1_out : out  STD_LOGIC_VECTOR (7 downto 0);
    58 --           Port2_out : out  STD_LOGIC_VECTOR (7 downto 0);
    59 --           Port3_out : out  STD_LOGIC_VECTOR (7 downto 0);
    60 --           Port4_out : out  STD_LOGIC_VECTOR (7 downto 0);
    61 --                        Port5_out : out  STD_LOGIC_VECTOR (7 downto 0);
    62 --           Port6_out : out  STD_LOGIC_VECTOR (7 downto 0);
    63 --           Port7_out : out  STD_LOGIC_VECTOR (7 downto 0);
    64 --           Port8_out : out  STD_LOGIC_VECTOR (7 downto 0);
    65 --                        Port9_out : out  STD_LOGIC_VECTOR (7 downto 0);
    66 --           Port10_out : out  STD_LOGIC_VECTOR (7 downto 0);
    67 --           Port11_out : out  STD_LOGIC_VECTOR (7 downto 0);
    68 --           Port12_out : out  STD_LOGIC_VECTOR (7 downto 0);
    69 --                        Port13_out : out  STD_LOGIC_VECTOR (7 downto 0);
    70 --           Port14_out : out  STD_LOGIC_VECTOR (7 downto 0);
    71 --           Port15_out : out  STD_LOGIC_VECTOR (7 downto 0);
    72 --           Port16_out : out  STD_LOGIC_VECTOR (7 downto 0);
     42
    7343                          -- signaux de controle
    7444                          data_in_en : in std_logic_vector(number_of_ports downto 1);
    … …  
    8757
    8858COMPONENT INPUT_PORT_MODULE
    89   generic(number_of_ports : positive := 4;
     59  generic(number_of_ports : positive := 8;
    9060                        Port_num: natural);
    9161    Port ( data_in : in  STD_LOGIC_VECTOR (7 downto 0);
    … …  
    12595                        );
    12696    Port (
    127                 --Port_in : in Typ_PortIO(1 to number_of_crossbar_ports);
    128                           Port1_in : in  STD_LOGIC_VECTOR (7 downto 0);
     97                clk : in  STD_LOGIC;
     98                        reset : in  STD_LOGIC;
     99                        Port1_in : in  STD_LOGIC_VECTOR (7 downto 0);
    129100           Port2_in : in  STD_LOGIC_VECTOR (7 downto 0);
    130101           Port3_in : in  STD_LOGIC_VECTOR (7 downto 0);
    … …  
    213184
    214185--declaration des signaux de connection entre les modules du switch
    215 --type port_connection_type is array(16 downto 1) of std_logic_vector(7 downto 1);
    216 --signal crossbar_port_in_connetion : port_connection_type;
    217 --signal crossbar_port_out_connetion :port_connection_type;
    218 --signal request_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
    219 --signal grant_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
    220 --signal priority_rotation_connection : std_logic_vector(number_of_ports downto 1);
    221 --signal fifo_out_full_connection : std_logic_vector(1 to number_of_ports);
    222 --signal crossbar_in_pulse(_connection : std_logic_vector(number_of_ports downto 1);
    223 --signal crossbar_out_pulse_connection : std_logic_vector(number_of_ports downto 1);
    224 --variable i,j : integer;
    225186
    226187Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
    … …  
    231192signal crossbar_in_port :  Typ_PortIO(1 to number_of_ports);
    232193
    233 --signal crossbar_in_port1 : std_logic_vector(7 downto 0);
    234 --signal crossbar_in_port2 : std_logic_vector(7 downto 0);
    235 --signal crossbar_in_port3 : std_logic_vector(7 downto 0);
    236 --signal crossbar_in_port4 : std_logic_vector(7 downto 0);
    237 --signal crossbar_in_port5 : std_logic_vector(7 downto 0);
    238 --signal crossbar_in_port6 : std_logic_vector(7 downto 0);
    239 --signal crossbar_in_port7 : std_logic_vector(7 downto 0);
    240 --signal crossbar_in_port8 : std_logic_vector(7 downto 0);
    241 --signal crossbar_in_port9 : std_logic_vector(7 downto 0);
    242 --signal crossbar_in_port10 : std_logic_vector(7 downto 0);
    243 --signal crossbar_in_port11 : std_logic_vector(7 downto 0);
    244 --signal crossbar_in_port12 : std_logic_vector(7 downto 0);
    245 --signal crossbar_in_port13 : std_logic_vector(7 downto 0);
    246 --signal crossbar_in_port14 : std_logic_vector(7 downto 0);
    247 --signal crossbar_in_port15 : std_logic_vector(7 downto 0);
    248 --signal crossbar_in_port16 : std_logic_vector(7 downto 0);
     194
    249195
    250196signal crossbar_out_port  :  Typ_PortIO(1 to number_of_ports);
    251 --signal crossbar_out_port1 : std_logic_vector(7 downto 0);
    252 --signal crossbar_out_port2 : std_logic_vector(7 downto 0);
    253 --signal crossbar_out_port3 : std_logic_vector(7 downto 0);
    254 --signal crossbar_out_port4 : std_logic_vector(7 downto 0);
    255 --signal crossbar_out_port5 : std_logic_vector(7 downto 0);
    256 --signal crossbar_out_port6 : std_logic_vector(7 downto 0);
    257 --signal crossbar_out_port7 : std_logic_vector(7 downto 0);
    258 --signal crossbar_out_port8 : std_logic_vector(7 downto 0);
    259 --signal crossbar_out_port9 : std_logic_vector(7 downto 0);
    260 --signal crossbar_out_port10 : std_logic_vector(7 downto 0);
    261 --signal crossbar_out_port11 : std_logic_vector(7 downto 0);
    262 --signal crossbar_out_port12 : std_logic_vector(7 downto 0);
    263 --signal crossbar_out_port13 : std_logic_vector(7 downto 0);
    264 --signal crossbar_out_port14 : std_logic_vector(7 downto 0);
    265 --signal crossbar_out_port15 : std_logic_vector(7 downto 0);
    266 --signal crossbar_out_port16 : std_logic_vector(7 downto 0);
     197
    267198
    268199signal crossbar_in_pulse  : std_logic_vector(number_of_ports downto 1);
    269 --signal crossbar_in_pulse1 : std_logic;
    270 --signal crossbar_in_pulse2 : std_logic;
    271 --signal crossbar_in_pulse3 : std_logic;
    272 --signal crossbar_in_pulse4 : std_logic;
    273 --signal crossbar_in_pulse5 : std_logic;
    274 --signal crossbar_in_pulse6 : std_logic;
    275 --signal crossbar_in_pulse7 : std_logic;
    276 --signal crossbar_in_pulse8 : std_logic;
    277 --signal crossbar_in_pulse9 : std_logic;
    278 --signal crossbar_in_pulse10 : std_logic;
    279 --signal crossbar_in_pulse11 : std_logic;
    280 --signal crossbar_in_pulse12 : std_logic;
    281 --signal crossbar_in_pulse13 : std_logic;
    282 --signal crossbar_in_pulse14 : std_logic;
    283 --signal crossbar_in_pulse15 : std_logic;
    284 --signal crossbar_in_pulse16 : std_logic;
     200
    285201
    286202signal crossbar_out_pulse  : std_logic_vector(number_of_ports downto 1);
    287 --signal crossbar_out_pulse1 : std_logic;
    288 --signal crossbar_out_pulse2 : std_logic;
    289 --signal crossbar_out_pulse3 : std_logic;
    290 --signal crossbar_out_pulse4 : std_logic;
    291 --signal crossbar_out_pulse5 : std_logic;
    292 --signal crossbar_out_pulse6 : std_logic;
    293 --signal crossbar_out_pulse7 : std_logic;
    294 --signal crossbar_out_pulse8 : std_logic;
    295 --signal crossbar_out_pulse9 : std_logic;
    296 --signal crossbar_out_pulse10 : std_logic;
    297 --signal crossbar_out_pulse11 : std_logic;
    298 --signal crossbar_out_pulse12 : std_logic;
    299 --signal crossbar_out_pulse13 : std_logic;
    300 --signal crossbar_out_pulse14 : std_logic;
    301 --signal crossbar_out_pulse15 : std_logic;
    302 --signal crossbar_out_pulse16 : std_logic;
     203
    303204
    304205
    … …  
    428329--j=number_of_ports*(i-1);
    429330PORTx4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    430 GENERIC MAP(number_of_ports =>4,Port_num=>i)
     331GENERIC MAP(number_of_ports =>number_of_ports,Port_num=>i)
    431332PORT MAP(
    432333   data_in => Port_in(i),
    … …  
    62816182GENERIC MAP(number_of_crossbar_ports =>2)
    62826183  PORT MAP(
     6184                reset => reset,
     6185     clk => clk,
    62836186   Port1_in => crossbar_in_port(1),
    62846187   Port2_in => crossbar_in_port(2),
    … …  
    63276230GENERIC MAP(number_of_crossbar_ports =>3)
    63286231  PORT MAP(
    6329    Port1_in => crossbar_in_port(1),
     6232                reset => reset,
     6233     clk => clk,
     6234        Port1_in => crossbar_in_port(1),
    63306235   Port2_in => crossbar_in_port(2),
    63316236   Port3_in => crossbar_in_port(3),
    … …  
    63756280GENERIC MAP(number_of_crossbar_ports =>4)
    63766281  PORT MAP(
     6282                reset => reset,
     6283     clk => clk, 
    63776284   Port1_in => crossbar_in_port(1),
    63786285   Port2_in => crossbar_in_port(2),
    … …  
    64256332GENERIC MAP(number_of_crossbar_ports =>5)
    64266333  PORT MAP(
     6334                reset => reset,
     6335     clk => clk,
    64276336   Port1_in => crossbar_in_port(1),
    64286337   Port2_in => crossbar_in_port(2),
    … …  
    64776386GENERIC MAP(number_of_crossbar_ports =>6)
    64786387  PORT MAP(
     6388 
     6389                reset => reset,
     6390     clk => clk,
    64796391   Port1_in => crossbar_in_port(1),
    64806392   Port2_in => crossbar_in_port(2),
    … …  
    65316443GENERIC MAP(number_of_crossbar_ports =>7)
    65326444  PORT MAP(
     6445                reset => reset,
     6446     clk => clk,
    65336447   Port1_in => crossbar_in_port(1),
    65346448   Port2_in => crossbar_in_port(2),
    … …  
    65876501GENERIC MAP(number_of_crossbar_ports =>8)
    65886502  PORT MAP(
     6503    reset => reset,
     6504   clk =>clk,
    65896505   Port1_in => crossbar_in_port(1),
    65906506   Port2_in => crossbar_in_port(2),
    … …  
    66456561GENERIC MAP(number_of_crossbar_ports =>9)
    66466562  PORT MAP(
     6563                reset => reset,
     6564     clk => clk,
    66476565   Port1_in => crossbar_in_port(1),
    66486566   Port2_in => crossbar_in_port(2),
    … …  
    67056623GENERIC MAP(number_of_crossbar_ports =>10)
    67066624  PORT MAP(
     6625        reset => reset,
     6626   clk => clk,
    67076627   Port1_in => crossbar_in_port(1),
    67086628   Port2_in => crossbar_in_port(2),
    … …  
    67676687GENERIC MAP(number_of_crossbar_ports =>11)
    67686688  PORT MAP(
     6689        reset => reset,
     6690   clk => clk,
    67696691   Port1_in => crossbar_in_port(1),
    67706692   Port2_in => crossbar_in_port(2),
    … …  
    68316753GENERIC MAP(number_of_crossbar_ports =>12)
    68326754  PORT MAP(
     6755        reset => reset,
     6756   clk => clk,
    68336757   Port1_in => crossbar_in_port(1),
    68346758   Port2_in => crossbar_in_port(2),
    … …  
    68976821GENERIC MAP(number_of_crossbar_ports =>13)
    68986822  PORT MAP(
     6823        reset => reset,
     6824   clk => clk,
    68996825   Port1_in => crossbar_in_port(1),
    69006826   Port2_in => crossbar_in_port(2),
    … …  
    69656891GENERIC MAP(number_of_crossbar_ports =>14)
    69666892  PORT MAP(
     6893        reset => reset,
     6894   clk => clk,
    69676895   Port1_in => crossbar_in_port(1),
    69686896   Port2_in => crossbar_in_port(2),
    … …  
    70356963GENERIC MAP(number_of_crossbar_ports =>15)
    70366964  PORT MAP(
     6965        reset => reset,
     6966   clk => clk,
    70376967   Port1_in => crossbar_in_port(1),
    70386968   Port2_in => crossbar_in_port(2),
    … …  
    71077037GENERIC MAP(number_of_crossbar_ports =>16)
    71087038  PORT MAP(
     7039        reset => reset,
     7040   clk => clk,
    71097041   Port1_in => crossbar_in_port(1),
    71107042   Port2_in => crossbar_in_port(2),
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