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Changeset 65 for PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Scheduler.vhd
- Timestamp:
- Apr 22, 2013, 11:35:33 AM (11 years ago)
- File:
-
- 1 edited
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PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Scheduler.vhd
r22 r65 42 42 43 43 architecture Behavioral of Scheduler is 44 -- signaux pour le pipeline; 45 signal Request_latch :STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1):=(others=>'0'); 46 signal Fifo_full_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'0'); 47 signal priority_rotation_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'1'); 48 44 49 -- composants du scheduler 45 46 -- composants du scheduler47 48 49 50 COMPONENT Scheduler2_2 50 51 PORT( … … 225 226 Inst_Scheduler2_2 : Scheduler2_2 226 227 PORT MAP( 228 Request => Request_latch, 229 Fifo_full => Fifo_full_latch, 230 clk => clk , 231 reset =>reset, 232 priority_rotation =>priority_rotation_latch, 233 port_grant =>port_grant); 234 end generate scheduler2x2; 235 236 --======================scheduler 3 ports======================= 237 238 scheduler3x3 : if number_of_ports = 3 generate 239 240 Inst_Scheduler3_3 : Scheduler3_3 241 PORT MAP( 242 Request => Request_latch, 243 Fifo_full => Fifo_full_latch, 244 clk => clk , 245 reset =>reset, 246 priority_rotation =>priority_rotation_latch, 247 port_grant =>port_grant); 248 end generate scheduler3x3; 249 250 --======================scheduler 4 ports======================= 251 252 scheduler4x4 : if number_of_ports = 4 generate 253 254 Inst_Scheduler4_4 : Scheduler4_4 255 PORT MAP( 256 Request => Request_latch, 257 Fifo_full => Fifo_full_latch, 258 clk => clk , 259 reset =>reset, 260 priority_rotation =>priority_rotation_latch, 261 port_grant =>port_grant); 262 end generate scheduler4x4; 263 264 --======================scheduler 5 ports======================= 265 266 scheduler5x5 : if number_of_ports = 5 generate 267 268 Inst_Scheduler5_5 : Scheduler5_5 269 PORT MAP( 227 270 Request => Request, 228 271 Fifo_full => Fifo_full, … … 231 274 priority_rotation =>priority_rotation, 232 275 port_grant =>port_grant); 233 end generate scheduler2x2; 234 235 --======================scheduler 3 ports======================= 236 237 scheduler3x3 : if number_of_ports = 3 generate 238 239 Inst_Scheduler3_3 : Scheduler3_3 276 end generate scheduler5x5; 277 278 --======================scheduler 6 ports======================= 279 280 scheduler6x6 : if number_of_ports = 6 generate 281 282 Inst_Scheduler6_6 : Scheduler6_6 283 PORT MAP( 284 Request => Request_latch, 285 Fifo_full => Fifo_full_latch, 286 clk => clk , 287 reset =>reset, 288 priority_rotation =>priority_rotation_latch, 289 port_grant =>port_grant); 290 end generate scheduler6x6; 291 292 --======================scheduler 7 ports======================= 293 294 scheduler7x7 : if number_of_ports = 7 generate 295 296 Inst_Scheduler7_7 : Scheduler7_7 297 PORT MAP( 298 Request => Request_latch, 299 Fifo_full => Fifo_full_latch, 300 clk => clk , 301 reset =>reset, 302 priority_rotation =>priority_rotation_latch, 303 port_grant =>port_grant); 304 end generate scheduler7x7; 305 306 --======================scheduler 8 ports======================= 307 308 scheduler8x8 : if number_of_ports = 8 generate 309 310 Inst_Scheduler8_8 : Scheduler8_8 311 PORT MAP( 312 Request => Request_latch, 313 Fifo_full => Fifo_full_latch, 314 clk => clk , 315 reset =>reset, 316 priority_rotation =>priority_rotation_latch, 317 port_grant =>port_grant); 318 end generate scheduler8x8; 319 320 --======================scheduler 9 ports======================= 321 322 scheduler9x9 : if number_of_ports = 9 generate 323 324 Inst_Scheduler9_9 : Scheduler9_9 325 PORT MAP( 326 Request => Request_latch, 327 Fifo_full => Fifo_full_latch, 328 clk => clk , 329 reset =>reset, 330 priority_rotation =>priority_rotation_latch, 331 port_grant =>port_grant); 332 end generate scheduler9x9; 333 334 --======================scheduler 10 ports======================= 335 336 scheduler10x10 : if number_of_ports = 10 generate 337 338 Inst_Scheduler10_10 : Scheduler10_10 240 339 PORT MAP( 241 340 Request => Request, … … 245 344 priority_rotation =>priority_rotation, 246 345 port_grant =>port_grant); 247 end generate scheduler 3x3;248 249 --======================scheduler 4ports=======================250 251 scheduler 4x4 : if number_of_ports = 4generate252 253 Inst_Scheduler 4_4 : Scheduler4_4346 end generate scheduler10x10; 347 348 --======================scheduler 11 ports======================= 349 350 scheduler11x11 : if number_of_ports = 11 generate 351 352 Inst_Scheduler11_11 : Scheduler11_11 254 353 PORT MAP( 255 354 Request => Request, … … 259 358 priority_rotation =>priority_rotation, 260 359 port_grant =>port_grant); 261 end generate scheduler4x4;262 263 --======================scheduler 5 ports=======================264 265 scheduler5x5 : if number_of_ports = 5 generate266 267 Inst_Scheduler5_5 : Scheduler5_5268 PORT MAP(269 Request => Request,270 Fifo_full => Fifo_full,271 clk => clk ,272 reset =>reset,273 priority_rotation =>priority_rotation,274 port_grant =>port_grant);275 end generate scheduler5x5;276 277 --======================scheduler 6 ports=======================278 279 scheduler6x6 : if number_of_ports = 6 generate280 281 Inst_Scheduler6_6 : Scheduler6_6282 PORT MAP(283 Request => Request,284 Fifo_full => Fifo_full,285 clk => clk ,286 reset =>reset,287 priority_rotation =>priority_rotation,288 port_grant =>port_grant);289 end generate scheduler6x6;290 291 --======================scheduler 7 ports=======================292 293 scheduler7x7 : if number_of_ports = 7 generate294 295 Inst_Scheduler7_7 : Scheduler7_7296 PORT MAP(297 Request => Request,298 Fifo_full => Fifo_full,299 clk => clk ,300 reset =>reset,301 priority_rotation =>priority_rotation,302 port_grant =>port_grant);303 end generate scheduler7x7;304 305 --======================scheduler 8 ports=======================306 307 scheduler8x8 : if number_of_ports = 8 generate308 309 Inst_Scheduler8_8 : Scheduler8_8310 PORT MAP(311 Request => Request,312 Fifo_full => Fifo_full,313 clk => clk ,314 reset =>reset,315 priority_rotation =>priority_rotation,316 port_grant =>port_grant);317 end generate scheduler8x8;318 319 --======================scheduler 9 ports=======================320 321 scheduler9x9 : if number_of_ports = 9 generate322 323 Inst_Scheduler9_9 : Scheduler9_9324 PORT MAP(325 Request => Request,326 Fifo_full => Fifo_full,327 clk => clk ,328 reset =>reset,329 priority_rotation =>priority_rotation,330 port_grant =>port_grant);331 end generate scheduler9x9;332 333 --======================scheduler 10 ports=======================334 335 scheduler10x10 : if number_of_ports = 10 generate336 337 Inst_Scheduler10_10 : Scheduler10_10338 PORT MAP(339 Request => Request,340 Fifo_full => Fifo_full,341 clk => clk ,342 reset =>reset,343 priority_rotation =>priority_rotation,344 port_grant =>port_grant);345 end generate scheduler10x10;346 347 --======================scheduler 11 ports=======================348 349 scheduler11x11 : if number_of_ports = 11 generate350 351 Inst_Scheduler11_11 : Scheduler11_11352 PORT MAP(353 Request => Request,354 Fifo_full => Fifo_full,355 clk => clk ,356 reset =>reset,357 priority_rotation =>priority_rotation,358 port_grant =>port_grant);359 360 end generate scheduler11x11; 360 361 … … 365 366 Inst_Scheduler12_12 : Scheduler12_12 366 367 PORT MAP( 367 Request => Request ,368 Fifo_full => Fifo_full ,369 clk => clk , 370 reset =>reset, 371 priority_rotation =>priority_rotation ,368 Request => Request_latch, 369 Fifo_full => Fifo_full_latch, 370 clk => clk , 371 reset =>reset, 372 priority_rotation =>priority_rotation_latch, 372 373 port_grant =>port_grant); 373 374 end generate scheduler12x12; … … 379 380 Inst_Scheduler13_13 : Scheduler13_13 380 381 PORT MAP( 381 Request => Request ,382 Fifo_full => Fifo_full ,383 clk => clk , 384 reset =>reset, 385 priority_rotation =>priority_rotation ,382 Request => Request_latch, 383 Fifo_full => Fifo_full_latch, 384 clk => clk , 385 reset =>reset, 386 priority_rotation =>priority_rotation_latch, 386 387 port_grant =>port_grant); 387 388 end generate scheduler13x13; … … 393 394 Inst_Scheduler14_14 : Scheduler14_14 394 395 PORT MAP( 395 Request => Request ,396 Fifo_full => Fifo_full ,397 clk => clk , 398 reset =>reset, 399 priority_rotation =>priority_rotation ,396 Request => Request_latch, 397 Fifo_full => Fifo_full_latch, 398 clk => clk , 399 reset =>reset, 400 priority_rotation =>priority_rotation_latch, 400 401 port_grant =>port_grant); 401 402 end generate scheduler14x14; … … 407 408 Inst_Scheduler15_15 : Scheduler15_15 408 409 PORT MAP( 409 Request => Request ,410 Fifo_full => Fifo_full ,411 clk => clk , 412 reset =>reset, 413 priority_rotation =>priority_rotation ,410 Request => Request_latch, 411 Fifo_full => Fifo_full_latch, 412 clk => clk , 413 reset =>reset, 414 priority_rotation =>priority_rotation_latch, 414 415 port_grant =>port_grant); 415 416 end generate scheduler15x15; … … 421 422 Inst_Scheduler16_16 : Scheduler16_16 422 423 PORT MAP( 423 Request => Request ,424 Fifo_full => Fifo_full ,425 clk => clk , 426 reset =>reset, 427 priority_rotation =>priority_rotation ,424 Request => Request_latch, 425 Fifo_full => Fifo_full_latch, 426 clk => clk , 427 reset =>reset, 428 priority_rotation =>priority_rotation_latch, 428 429 port_grant =>port_grant); 429 430 end generate scheduler16x16; 430 431 Sched:process (clk,reset) 432 begin 433 if rising_edge(clk) then 434 if reset='1' then 435 request_latch<=(others=>'0'); 436 Fifo_full_latch<=(others=>'0'); 437 priority_rotation_latch<=(others=>'1'); 438 else 439 request_latch<=request; 440 Fifo_full_latch<=fifo_full; 441 priority_rotation_latch<=priority_rotation; 442 end if; 443 end if; 444 end process sched; 431 445 end Behavioral; 432 446
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