Ignore:
Timestamp:
Dec 20, 2013, 7:55:55 PM (11 years ago)
Author:
rolagamo
Message:
 
File:
1 edited

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  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.xise

    r64 r70  
    302302    </file>
    303303    <file xil_pn:name="Hold_FSM.vhd" xil_pn:type="FILE_VHDL">
     304      <association xil_pn:name="BehavioralSimulation"/>
     305      <association xil_pn:name="Implementation"/>
     306    </file>
     307    <file xil_pn:name="HT_process.vhd" xil_pn:type="FILE_VHDL">
     308      <association xil_pn:name="BehavioralSimulation"/>
     309      <association xil_pn:name="Implementation"/>
     310    </file>
     311    <file xil_pn:name="Ex5_FSM.vhd" xil_pn:type="FILE_VHDL">
     312      <association xil_pn:name="BehavioralSimulation"/>
     313      <association xil_pn:name="Implementation"/>
     314    </file>
     315    <file xil_pn:name="SetBit.vhd" xil_pn:type="FILE_VHDL">
    304316      <association xil_pn:name="BehavioralSimulation"/>
    305317      <association xil_pn:name="Implementation"/>
    … …  
    357369    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
    358370    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
     371    <property xil_pn:name="Custom Do File Behavioral" xil_pn:value="wave_mpi.do" xil_pn:valueState="non-default"/>
    359372    <property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="MultiTest.wcfg" xil_pn:valueState="non-default"/>
    360373    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    … …  
    363376    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    364377    <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    365     <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
     378    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
    366379    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
    367380    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
    … …  
    454467    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
    455468    <property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
    456     <property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
     469    <property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="true" xil_pn:valueState="non-default"/>
    457470    <property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
    458471    <property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    514527    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
    515528    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
    516     <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
     529    <property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="default"/>
    517530    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    518531    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    533546    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
    534547    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
    535     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
     548    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    536549    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
    537550    <property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    592605    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    593606    <property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
    594     <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="200 ns" xil_pn:valueState="non-default"/>
     607    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    595608    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    596     <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
     609    <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000 ns" xil_pn:valueState="non-default"/>
    597610    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    598611    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    599     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     612    <property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="non-default"/>
    600613    <property xil_pn:name="Simulator Path" xil_pn:value="../CORE_MPI" xil_pn:valueState="non-default"/>
    601614    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
    … …  
    613626    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
    614627    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    615     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
     628    <property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="default"/>
    616629    <property xil_pn:name="Target UCF File Name" xil_pn:value="MPI_NOC.ucf" xil_pn:valueState="non-default"/>
    617630    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
    … …  
    625638    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
    626639    <property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
    627     <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
     640    <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="true" xil_pn:valueState="non-default"/>
    628641    <property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
    629642    <property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
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