Ignore:
Timestamp:
Jan 15, 2014, 2:40:01 AM (11 years ago)
Author:
rolagamo
Message:
 
Location:
PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MPI_CORE_COMPONENTS.projectmgr

    r72 r74  
    363363      </ClosedNodes>
    364364      <SelectedItems>
    365          <SelectedItem>MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd)</SelectedItem>
    366       </SelectedItems>
    367       <ScrollbarPosition orientation="vertical" >26</ScrollbarPosition>
     365         <SelectedItem>xc6slx75-3csg484</SelectedItem>
     366      </SelectedItems>
     367      <ScrollbarPosition orientation="vertical" >1</ScrollbarPosition>
    368368      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    369369      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000035b000000020000000000000000000000000000000064ffffffff0000008100000000000000020000035b0000000100000000000000000000000100000000</ViewHeaderState>
    370370      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    371       <CurrentItem>MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd)</CurrentItem>
     371      <CurrentItem>xc6slx75-3csg484</CurrentItem>
    372372   </ItemView>
    373373   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
    … …  
    376376         <ClosedNode>Configure Target Device</ClosedNode>
    377377         <ClosedNode>Implement Design/Map</ClosedNode>
    378          <ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
    379378         <ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
    380379         <ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode>
    … …  
    383382      </ClosedNodes>
    384383      <SelectedItems>
    385          <SelectedItem>Implement Design</SelectedItem>
    386       </SelectedItems>
    387       <ScrollbarPosition orientation="vertical" >1</ScrollbarPosition>
     384         <SelectedItem>View/Edit Routed Design (FPGA Editor)</SelectedItem>
     385      </SelectedItems>
     386      <ScrollbarPosition orientation="vertical" >17</ScrollbarPosition>
    388387      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    389388      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000014b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000014b0000000100000000</ViewHeaderState>
    390389      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    391       <CurrentItem>Implement Design</CurrentItem>
     390      <CurrentItem>View/Edit Routed Design (FPGA Editor)</CurrentItem>
    392391   </ItemView>
    393392   <ItemView guiview="File" >
    … …  
    396395      </ClosedNodes>
    397396      <SelectedItems>
    398          <SelectedItem>C:\Core MPI\CORE_MPI\SWITCH_GEN.ucf</SelectedItem>
    399       </SelectedItems>
    400       <ScrollbarPosition orientation="vertical" >51</ScrollbarPosition>
     397         <SelectedItem>C:\Core MPI\CORE_MPI\EX4_FSM.vhd</SelectedItem>
     398      </SelectedItems>
     399      <ScrollbarPosition orientation="vertical" >12</ScrollbarPosition>
    401400      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    402401      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000002010000000000000000000000000000000000000307000000040101000100000000000000000000000064ffffffff000000810000000000000004000001f90000000100000000000000440000000100000000000000660000000100000000000000640000000100000000</ViewHeaderState>
    403402      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    404       <CurrentItem>C:\Core MPI\CORE_MPI\SWITCH_GEN.ucf</CurrentItem>
     403      <CurrentItem>C:\Core MPI\CORE_MPI\EX4_FSM.vhd</CurrentItem>
    405404   </ItemView>
    406405   <ItemView guiview="Library" >
    … …  
    413412      <ScrollbarPosition orientation="vertical" >50</ScrollbarPosition>
    414413      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    415       <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000103000000010001000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
     414      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000014b000000010001000100000000000000000000000064ffffffff0000008100000000000000010000014b0000000100000000</ViewHeaderState>
    416415      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    417416      <CurrentItem>C:\Core MPI\CORE_MPI\MultiMPITest.vhd</CurrentItem>
    … …  
    423422      </ClosedNodes>
    424423      <SelectedItems>
    425          <SelectedItem/>
    426       </SelectedItems>
    427       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
    428       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    429       <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000228000000010000000100000000000000000000000064ffffffff000000810000000000000001000002280000000100000000</ViewHeaderState>
    430       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    431       <CurrentItem/>
     424         <SelectedItem></SelectedItem>
     425      </SelectedItems>
     426      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
     427      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
     428      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
     429      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
     430      <CurrentItem></CurrentItem>
    432431   </ItemView>
    433432   <ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
    … …  
    540539         <SelectedItem>mpi_test - behavior (C:/Core MPI/CORE_MPI/mpi_test.vhd)</SelectedItem>
    541540      </SelectedItems>
    542       <ScrollbarPosition orientation="vertical" >9</ScrollbarPosition>
     541      <ScrollbarPosition orientation="vertical" >8</ScrollbarPosition>
    543542      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    544543      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002f3000000020000000000000000000000000000000064ffffffff000000810000000000000002000002f30000000100000000000000000000000100000000</ViewHeaderState>

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MultiMPITest.xreport

    r72 r74  
    22<report-views version="2.0" >
    33 <header>
    4   <DateModified>2013-12-30T18:29:08</DateModified>
    5   <ModuleName>SWITCH_GEN</ModuleName>
    6   <SummaryTimeStamp>2013-12-21T12:27:20</SummaryTimeStamp>
     4  <DateModified>2014-01-14T19:54:07</DateModified>
     5  <ModuleName>CORE_MPI</ModuleName>
     6  <SummaryTimeStamp>2014-01-14T19:51:12</SummaryTimeStamp>
    77  <SavedFilePath>C:/Core MPI/CORE_MPI/iseconfig/MultiMPITest.xreport</SavedFilePath>
    88  <ImplementationReportsDirectory>C:/Core MPI/CORE_MPI\</ImplementationReportsDirectory>
    9   <DateInitialized>2013-06-15T13:06:16</DateInitialized>
     9  <DateInitialized>2014-01-14T19:22:02</DateInitialized>
    1010  <EnableMessageFiltering>false</EnableMessageFiltering>
    1111 </header>
    1212 <body>
    1313  <viewgroup label="Design Overview" >
    14    <view inputState="Unknown" program="implementation" ShowPartitionData="false" ExpandConstraints="true" type="FPGASummary" file="SWITCH_GEN_summary.html" label="Summary" ExpandClockNets="true" ExpandWarnings="true" >
     14   <view inputState="Unknown" program="implementation" ShowPartitionData="false" ExpandConstraints="false" type="FPGASummary" file="CORE_MPI_summary.html" label="Summary" ExpandClockNets="false" ExpandWarnings="true" >
    1515    <toc-item title="Design Overview" target="Design Overview" />
    1616    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
    … …  
    2020    <table-item tableState="CollapsedTable" tableKey="CurrentWarnings" />
    2121    <table-item tableState="CollapsedTable" tableKey="CurrentWarnings" />
    22     <table-item tableState="ExpandedTable" tableKey="DeviceUtilizationSummary" />
     22    <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" />
    2323    <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" />
    2424    <table-item tableState="ExpandedTable" tableKey="SecondaryReports" />
    2525    <table-item tableState="ExpandedTable" tableKey="DetailedReports" />
    2626   </view>
    27    <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="SWITCH_GEN_envsettings.html" label="System Settings" />
    28    <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="SWITCH_GEN_map.xrpt" showConstraints="0" label="IOB Properties" />
    29    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="SWITCH_GEN_map.xrpt" label="Control Set Information" />
    30    <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="SWITCH_GEN_map.xrpt" label="Module Level Utilization" />
    31    <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="SWITCH_GEN.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
    32    <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="SWITCH_GEN_par.xrpt" showConstraints="0" label="Pinout Report" />
    33    <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="SWITCH_GEN_par.xrpt" showConstraints="0" label="Clock Report" />
    34    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="SWITCH_GEN.twx" label="Static Timing" />
    35    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/fit/report.htm" label="CPLD Fitter Report" />
    36    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/tim/report.htm" label="CPLD Timing Report" />
     27   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="CORE_MPI_envsettings.html" label="System Settings" />
     28   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="CORE_MPI_map.xrpt" showConstraints="0" label="IOB Properties" />
     29   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="CORE_MPI_map.xrpt" label="Control Set Information" />
     30   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="CORE_MPI_map.xrpt" label="Module Level Utilization" />
     31   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="CORE_MPI.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
     32   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="CORE_MPI_par.xrpt" showConstraints="0" label="Pinout Report" />
     33   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="CORE_MPI_par.xrpt" showConstraints="0" label="Clock Report" />
     34   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="CORE_MPI.twx" label="Static Timing" />
     35   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="CORE_MPI_html/fit/report.htm" label="CPLD Fitter Report" />
     36   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="CORE_MPI_html/tim/report.htm" label="CPLD Timing Report" />
    3737  </viewgroup>
    3838  <viewgroup label="XPS Errors and Warnings" >
    … …  
    4747   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
    4848   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
    49    <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="SWITCH_GEN.log" label="System Log File" />
     49   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="CORE_MPI.log" label="System Log File" />
    5050  </viewgroup>
    5151  <viewgroup label="Errors and Warnings" >
    … …  
    6363  </viewgroup>
    6464  <viewgroup label="Detailed Reports" >
    65    <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="SWITCH_GEN.syr" label="Synthesis Report" >
     65   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="CORE_MPI.syr" label="Synthesis Report" >
    6666    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
    6767    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
    … …  
    8989    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
    9090   </view>
    91    <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.srr" label="Synplify Report" />
    92    <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.prec_log" label="Precision Report" />
    93    <view inputState="Synthesized" program="ngdbuild" type="Report" file="SWITCH_GEN.bld" label="Translation Report" >
     91   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="CORE_MPI.srr" label="Synplify Report" />
     92   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="CORE_MPI.prec_log" label="Precision Report" />
     93   <view inputState="Synthesized" program="ngdbuild" type="Report" file="CORE_MPI.bld" label="Translation Report" >
    9494    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    9595    <toc-item title="Command Line" target="Command Line:" />
    … …  
    9797    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
    9898   </view>
    99    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN_map.mrp" label="Map Report" >
     99   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="CORE_MPI_map.mrp" label="Map Report" >
    100100    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    101101    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
    … …  
    113113    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
    114114   </view>
    115    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.par" label="Place and Route Report" >
     115   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="CORE_MPI.par" label="Place and Route Report" >
    116116    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    117117    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
    … …  
    122122    <toc-item title="Final Summary" target="Peak Memory Usage:" />
    123123   </view>
    124    <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.twr" label="Post-PAR Static Timing Report" >
     124   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="CORE_MPI.twr" label="Post-PAR Static Timing Report" >
    125125    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    126126    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    … …  
    133133    <toc-item title="Trace Settings" target="Trace Settings:" />
    134134   </view>
    135    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.rpt" label="CPLD Fitter Report (Text)" >
     135   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="CORE_MPI.rpt" label="CPLD Fitter Report (Text)" >
    136136    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
    137137    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
    … …  
    139139    <toc-item title="Global Resources" target="** Global Control Resources **" />
    140140   </view>
    141    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.tim" label="CPLD Timing Report (Text)" >
     141   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="CORE_MPI.tim" label="CPLD Timing Report (Text)" >
    142142    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
    143143    <toc-item title="Performance Summary" target="Performance Summary:" />
    144144   </view>
    145    <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="SWITCH_GEN.pwr" label="Power Report" >
     145   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="CORE_MPI.pwr" label="Power Report" >
    146146    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    147147    <toc-item title="Power summary" target="Power summary" />
    148148    <toc-item title="Thermal summary" target="Thermal summary" />
    149149   </view>
    150    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.bgn" label="Bitgen Report" >
     150   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="CORE_MPI.bgn" label="Bitgen Report" >
    151151    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    152152    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
    … …  
    156156  <viewgroup label="Secondary Reports" >
    157157   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
    158    <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/SWITCH_GEN_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
    159     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    160    </view>
    161    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/SWITCH_GEN_translate.nlf" label="Post-Translate Simulation Model Report" >
    162     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    163    </view>
    164    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
    165    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN_map.map" label="Map Log File" >
     158   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/CORE_MPI_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
     159    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     160   </view>
     161   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/CORE_MPI_translate.nlf" label="Post-Translate Simulation Model Report" >
     162    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     163   </view>
     164   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
     165   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="CORE_MPI_map.map" label="Map Log File" >
    166166    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    167167    <toc-item title="Design Information" target="Design Information" />
    … …  
    169169   </view>
    170170   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
    171    <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.twr" label="Post-Map Static Timing Report" >
     171   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_preroute.twr" label="Post-Map Static Timing Report" >
    172172    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    173173    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    … …  
    180180    <toc-item title="Trace Settings" target="Trace Settings:" />
    181181   </view>
    182    <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/SWITCH_GEN_map.nlf" label="Post-Map Simulation Model Report" />
    183    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_map.psr" label="Physical Synthesis Report" >
    184     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    185    </view>
    186    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="SWITCH_GEN_pad.txt" label="Pad Report" >
    187     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    188    </view>
    189    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN.unroutes" label="Unroutes Report" >
    190     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    191    </view>
    192    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.tsi" label="Post-Map Constraints Interaction Report" >
    193     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    194    </view>
    195    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.grf" label="Guide Results Report" />
    196    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.dly" label="Asynchronous Delay Report" />
    197    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.clk_rgn" label="Clock Region Report" />
    198    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.tsi" label="Post-Place and Route Constraints Interaction Report" >
    199     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    200    </view>
    201    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
    202    <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/SWITCH_GEN_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
    203    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_sta.nlf" label="Primetime Netlist Report" >
    204     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    205    </view>
    206    <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.ibs" label="IBIS Model" >
     182   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/CORE_MPI_map.nlf" label="Post-Map Simulation Model Report" />
     183   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_map.psr" label="Physical Synthesis Report" >
     184    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     185   </view>
     186   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="CORE_MPI_pad.txt" label="Pad Report" >
     187    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     188   </view>
     189   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="CORE_MPI.unroutes" label="Unroutes Report" >
     190    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     191   </view>
     192   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_preroute.tsi" label="Post-Map Constraints Interaction Report" >
     193    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     194   </view>
     195   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.grf" label="Guide Results Report" />
     196   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.dly" label="Asynchronous Delay Report" />
     197   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.clk_rgn" label="Clock Region Report" />
     198   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.tsi" label="Post-Place and Route Constraints Interaction Report" >
     199    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     200   </view>
     201   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
     202   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/CORE_MPI_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
     203   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_sta.nlf" label="Primetime Netlist Report" >
     204    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     205   </view>
     206   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.ibs" label="IBIS Model" >
    207207    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
    208208    <toc-item title="Component" target="Component " />
    209209   </view>
    210    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lck" label="Back-annotate Pin Report" >
     210   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.lck" label="Back-annotate Pin Report" >
    211211    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
    212212    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
    213213   </view>
    214    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lpc" label="Locked Pin Constraints" >
     214   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.lpc" label="Locked Pin Constraints" >
    215215    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
    216216    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
    217217   </view>
    218    <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/SWITCH_GEN_timesim.nlf" label="Post-Fit Simulation Model Report" />
     218   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/CORE_MPI_timesim.nlf" label="Post-Fit Simulation Model Report" />
    219219   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
    220220   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
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