Ignore:
Timestamp:
Jan 17, 2014, 5:04:00 PM (11 years ago)
Author:
rolagamo
Message:
 
Location:
PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MPI_CORE_COMPONENTS.projectmgr

    r74 r76  
    1717         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo1 - FIFO_64_FWFT - Behavioral</ClosedNode>
    1818         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo2 - FIFO_64_FWFT - Behavioral</ClosedNode>
     19         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/MPI_CORE_EX2_FSM - EX2_FSM - Behavioral</ClosedNode>
     20         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/sw_gen1 - SWITCH_GEN - Behavioral</ClosedNode>
    1921         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen - SWITCH_GEN - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
    2022         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen - SWITCH_GEN - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
    … …  
    187189         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/PE3 - PE - Behavioral</ClosedNode>
    188190         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/CORE_SCHEDULER - MPI_CORE_SCHEDULER - Behavioral</ClosedNode>
     191         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/MPI_PKG</ClosedNode>
     192         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/sw_gen1 - SWITCH_GEN - Behavioral</ClosedNode>
    189193         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral</ClosedNode>
    190194         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
    … …  
    243247         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/conversions</ClosedNode>
    244248         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd</ClosedNode>
     249         <ClosedNode>/Unassigned User Library Modules</ClosedNode>
    245250         <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral</ClosedNode>
    246251         <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
    … …  
    378383         <ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
    379384         <ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode>
    380          <ClosedNode>Implement Design/Place &amp; Route/Generate Post-Place &amp; Route Static Timing</ClosedNode>
    381          <ClosedNode>User Constraints</ClosedNode>
    382       </ClosedNodes>
    383       <SelectedItems>
    384          <SelectedItem>View/Edit Routed Design (FPGA Editor)</SelectedItem>
    385       </SelectedItems>
    386       <ScrollbarPosition orientation="vertical" >17</ScrollbarPosition>
     385      </ClosedNodes>
     386      <SelectedItems>
     387         <SelectedItem>Synthesize - XST</SelectedItem>
     388      </SelectedItems>
     389      <ScrollbarPosition orientation="vertical" >2</ScrollbarPosition>
    387390      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    388391      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000014b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000014b0000000100000000</ViewHeaderState>
    389392      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    390       <CurrentItem>View/Edit Routed Design (FPGA Editor)</CurrentItem>
     393      <CurrentItem>Synthesize - XST</CurrentItem>
    391394   </ItemView>
    392395   <ItemView guiview="File" >
    … …  
    395398      </ClosedNodes>
    396399      <SelectedItems>
    397          <SelectedItem>C:\Core MPI\CORE_MPI\EX4_FSM.vhd</SelectedItem>
    398       </SelectedItems>
    399       <ScrollbarPosition orientation="vertical" >12</ScrollbarPosition>
     400         <SelectedItem>C:\Core MPI\CORE_MPI\MultiMPITest.ucf</SelectedItem>
     401      </SelectedItems>
     402      <ScrollbarPosition orientation="vertical" >52</ScrollbarPosition>
    400403      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    401404      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000002010000000000000000000000000000000000000307000000040101000100000000000000000000000064ffffffff000000810000000000000004000001f90000000100000000000000440000000100000000000000660000000100000000000000640000000100000000</ViewHeaderState>
    402405      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    403       <CurrentItem>C:\Core MPI\CORE_MPI\EX4_FSM.vhd</CurrentItem>
     406      <CurrentItem>C:\Core MPI\CORE_MPI\MultiMPITest.ucf</CurrentItem>
    404407   </ItemView>
    405408   <ItemView guiview="Library" >
    … …  
    412415      <ScrollbarPosition orientation="vertical" >50</ScrollbarPosition>
    413416      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    414       <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000014b000000010001000100000000000000000000000064ffffffff0000008100000000000000010000014b0000000100000000</ViewHeaderState>
     417      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000103000000010001000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
    415418      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    416419      <CurrentItem>C:\Core MPI\CORE_MPI\MultiMPITest.vhd</CurrentItem>
    … …  
    419422      <ClosedNodes>
    420423         <ClosedNodesVersion>1</ClosedNodesVersion>
    421          <ClosedNode>Design Utilities</ClosedNode>
    422       </ClosedNodes>
    423       <SelectedItems>
    424          <SelectedItem></SelectedItem>
     424         <ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode>
     425      </ClosedNodes>
     426      <SelectedItems>
     427         <SelectedItem>Design Utilities</SelectedItem>
    425428      </SelectedItems>
    426429      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
    … …  
    428431      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
    429432      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    430       <CurrentItem></CurrentItem>
     433      <CurrentItem>Design Utilities</CurrentItem>
    431434   </ItemView>
    432435   <ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
    … …  
    442445         <ClosedNode>/FIFO - TOP_HIER C:|Core MPI|CORE_MPI|FIfo_mem.vhd</ClosedNode>
    443446         <ClosedNode>/Image_Pkg C:|Core MPI|CORE_MPI|image_pkg.vhd</ClosedNode>
    444          <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural</ClosedNode>
    445447         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/CORE_SCHEDULER - MPI_CORE_SCHEDULER - Behavioral</ClosedNode>
    446448         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo1 - FIFO_64_FWFT - Behavioral</ClosedNode>
    447449         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo2 - FIFO_64_FWFT - Behavioral</ClosedNode>
     450         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/MPI_CORE_EX2_FSM - EX2_FSM - Behavioral</ClosedNode>
    448451         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral</ClosedNode>
    449452         <ClosedNode>/MPI_NOC - structural C:|Core MPI|CORE_MPI|MPI_NOC.vhd</ClosedNode>
    … …  
    537540      </ClosedNodes>
    538541      <SelectedItems>
    539          <SelectedItem>mpi_test - behavior (C:/Core MPI/CORE_MPI/mpi_test.vhd)</SelectedItem>
    540       </SelectedItems>
    541       <ScrollbarPosition orientation="vertical" >8</ScrollbarPosition>
    542       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    543       <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002f3000000020000000000000000000000000000000064ffffffff000000810000000000000002000002f30000000100000000000000000000000100000000</ViewHeaderState>
    544       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    545       <CurrentItem>mpi_test - behavior (C:/Core MPI/CORE_MPI/mpi_test.vhd)</CurrentItem>
     542         <SelectedItem>Unassigned User Library Modules</SelectedItem>
     543      </SelectedItems>
     544      <ScrollbarPosition orientation="vertical" >2</ScrollbarPosition>
     545      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
     546      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000035b000000020000000000000000000000000000000064ffffffff0000008100000000000000020000035b0000000100000000000000000000000100000000</ViewHeaderState>
     547      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
     548      <CurrentItem>Unassigned User Library Modules</CurrentItem>
    546549   </ItemView>
    547550   <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
    … …  
    551554      </ClosedNodes>
    552555      <SelectedItems>
    553          <SelectedItem/>
     556         <SelectedItem>Update All Schematic Files</SelectedItem>
    554557      </SelectedItems>
    555558      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
    … …  
    557560      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
    558561      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    559       <CurrentItem/>
     562      <CurrentItem>Update All Schematic Files</CurrentItem>
    560563   </ItemView>
    561564   <ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
    … …  
    564567      </ClosedNodes>
    565568      <SelectedItems>
    566          <SelectedItem>ModelSim Simulator</SelectedItem>
     569         <SelectedItem></SelectedItem>
    567570      </SelectedItems>
    568571      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
    … …  
    570573      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
    571574      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    572       <CurrentItem>ModelSim Simulator</CurrentItem>
     575      <CurrentItem></CurrentItem>
    573576   </ItemView>
    574577   <SourceProcessView>000000ff0000000000000002000000d1000000d101000000050100000002</SourceProcessView>
    575    <CurrentView>Behavioral Simulation</CurrentView>
     578   <CurrentView>Implementation</CurrentView>
    576579   <ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_PACKAGE_DECL" guiview="Process" >
    577580      <ClosedNodes>
    … …  
    762765         <ClosedNodesVersion>1</ClosedNodesVersion>
    763766      </ClosedNodes>
    764       <SelectedItems/>
    765       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
    766       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    767       <ViewHeaderState orientation="horizontal" />
    768       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    769       <CurrentItem/>
     767      <SelectedItems>
     768         <SelectedItem></SelectedItem>
     769      </SelectedItems>
     770      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
     771      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
     772      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
     773      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
     774      <CurrentItem></CurrentItem>
     775   </ItemView>
     776   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_PACKAGE_BODY" guiview="Process" >
     777      <ClosedNodes>
     778         <ClosedNodesVersion>1</ClosedNodesVersion>
     779      </ClosedNodes>
     780      <SelectedItems>
     781         <SelectedItem></SelectedItem>
     782      </SelectedItems>
     783      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
     784      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
     785      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
     786      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
     787      <CurrentItem></CurrentItem>
     788   </ItemView>
     789   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_PACKAGE_DECL" guiview="Process" >
     790      <ClosedNodes>
     791         <ClosedNodesVersion>1</ClosedNodesVersion>
     792      </ClosedNodes>
     793      <SelectedItems>
     794         <SelectedItem></SelectedItem>
     795      </SelectedItems>
     796      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
     797      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
     798      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
     799      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
     800      <CurrentItem></CurrentItem>
    770801   </ItemView>
    771802</Project>

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MultiMPITest.xreport

    r74 r76  
    22<report-views version="2.0" >
    33 <header>
    4   <DateModified>2014-01-14T19:54:07</DateModified>
    5   <ModuleName>CORE_MPI</ModuleName>
    6   <SummaryTimeStamp>2014-01-14T19:51:12</SummaryTimeStamp>
     4  <DateModified>2014-01-15T10:32:39</DateModified>
     5  <ModuleName>MultiMPITest</ModuleName>
     6  <SummaryTimeStamp>2014-01-15T10:32:39</SummaryTimeStamp>
    77  <SavedFilePath>C:/Core MPI/CORE_MPI/iseconfig/MultiMPITest.xreport</SavedFilePath>
    88  <ImplementationReportsDirectory>C:/Core MPI/CORE_MPI\</ImplementationReportsDirectory>
    9   <DateInitialized>2014-01-14T19:22:02</DateInitialized>
     9  <DateInitialized>2014-01-15T10:26:54</DateInitialized>
    1010  <EnableMessageFiltering>false</EnableMessageFiltering>
    1111 </header>
    1212 <body>
    1313  <viewgroup label="Design Overview" >
    14    <view inputState="Unknown" program="implementation" ShowPartitionData="false" ExpandConstraints="false" type="FPGASummary" file="CORE_MPI_summary.html" label="Summary" ExpandClockNets="false" ExpandWarnings="true" >
     14   <view inputState="Unknown" program="implementation" ShowPartitionData="false" ExpandConstraints="false" type="FPGASummary" file="MultiMPITest_summary.html" label="Summary" ExpandClockNets="false" ExpandWarnings="true" >
    1515    <toc-item title="Design Overview" target="Design Overview" />
    1616    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
    … …  
    2525    <table-item tableState="ExpandedTable" tableKey="DetailedReports" />
    2626   </view>
    27    <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="CORE_MPI_envsettings.html" label="System Settings" />
    28    <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="CORE_MPI_map.xrpt" showConstraints="0" label="IOB Properties" />
    29    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="CORE_MPI_map.xrpt" label="Control Set Information" />
    30    <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="CORE_MPI_map.xrpt" label="Module Level Utilization" />
    31    <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="CORE_MPI.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
    32    <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="CORE_MPI_par.xrpt" showConstraints="0" label="Pinout Report" />
    33    <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="CORE_MPI_par.xrpt" showConstraints="0" label="Clock Report" />
    34    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="CORE_MPI.twx" label="Static Timing" />
    35    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="CORE_MPI_html/fit/report.htm" label="CPLD Fitter Report" />
    36    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="CORE_MPI_html/tim/report.htm" label="CPLD Timing Report" />
     27   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="MultiMPITest_envsettings.html" label="System Settings" />
     28   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="MultiMPITest_map.xrpt" showConstraints="0" label="IOB Properties" />
     29   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="MultiMPITest_map.xrpt" label="Control Set Information" />
     30   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="MultiMPITest_map.xrpt" label="Module Level Utilization" />
     31   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="MultiMPITest.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
     32   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="MultiMPITest_par.xrpt" showConstraints="0" label="Pinout Report" />
     33   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="MultiMPITest_par.xrpt" showConstraints="0" label="Clock Report" />
     34   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="MultiMPITest.twx" label="Static Timing" />
     35   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="MultiMPITest_html/fit/report.htm" label="CPLD Fitter Report" />
     36   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="MultiMPITest_html/tim/report.htm" label="CPLD Timing Report" />
    3737  </viewgroup>
    3838  <viewgroup label="XPS Errors and Warnings" >
    … …  
    4747   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
    4848   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
    49    <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="CORE_MPI.log" label="System Log File" />
     49   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="MultiMPITest.log" label="System Log File" />
    5050  </viewgroup>
    5151  <viewgroup label="Errors and Warnings" >
    … …  
    6363  </viewgroup>
    6464  <viewgroup label="Detailed Reports" >
    65    <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="CORE_MPI.syr" label="Synthesis Report" >
     65   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="MultiMPITest.syr" label="Synthesis Report" >
    6666    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
    6767    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
    … …  
    8989    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
    9090   </view>
    91    <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="CORE_MPI.srr" label="Synplify Report" />
    92    <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="CORE_MPI.prec_log" label="Precision Report" />
    93    <view inputState="Synthesized" program="ngdbuild" type="Report" file="CORE_MPI.bld" label="Translation Report" >
     91   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="MultiMPITest.srr" label="Synplify Report" />
     92   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="MultiMPITest.prec_log" label="Precision Report" />
     93   <view inputState="Synthesized" program="ngdbuild" type="Report" file="MultiMPITest.bld" label="Translation Report" >
    9494    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    9595    <toc-item title="Command Line" target="Command Line:" />
    … …  
    9797    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
    9898   </view>
    99    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="CORE_MPI_map.mrp" label="Map Report" >
     99   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="MultiMPITest_map.mrp" label="Map Report" >
    100100    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    101101    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
    … …  
    113113    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
    114114   </view>
    115    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="CORE_MPI.par" label="Place and Route Report" >
     115   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="MultiMPITest.par" label="Place and Route Report" >
    116116    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    117117    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
    … …  
    122122    <toc-item title="Final Summary" target="Peak Memory Usage:" />
    123123   </view>
    124    <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="CORE_MPI.twr" label="Post-PAR Static Timing Report" >
     124   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="MultiMPITest.twr" label="Post-PAR Static Timing Report" >
    125125    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    126126    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    … …  
    133133    <toc-item title="Trace Settings" target="Trace Settings:" />
    134134   </view>
    135    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="CORE_MPI.rpt" label="CPLD Fitter Report (Text)" >
     135   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="MultiMPITest.rpt" label="CPLD Fitter Report (Text)" >
    136136    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
    137137    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
    … …  
    139139    <toc-item title="Global Resources" target="** Global Control Resources **" />
    140140   </view>
    141    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="CORE_MPI.tim" label="CPLD Timing Report (Text)" >
     141   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="MultiMPITest.tim" label="CPLD Timing Report (Text)" >
    142142    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
    143143    <toc-item title="Performance Summary" target="Performance Summary:" />
    144144   </view>
    145    <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="CORE_MPI.pwr" label="Power Report" >
     145   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="MultiMPITest.pwr" label="Power Report" >
    146146    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    147147    <toc-item title="Power summary" target="Power summary" />
    148148    <toc-item title="Thermal summary" target="Thermal summary" />
    149149   </view>
    150    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="CORE_MPI.bgn" label="Bitgen Report" >
     150   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="MultiMPITest.bgn" label="Bitgen Report" >
    151151    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    152152    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
    … …  
    156156  <viewgroup label="Secondary Reports" >
    157157   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
    158    <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/CORE_MPI_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
    159     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    160    </view>
    161    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/CORE_MPI_translate.nlf" label="Post-Translate Simulation Model Report" >
    162     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    163    </view>
    164    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
    165    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="CORE_MPI_map.map" label="Map Log File" >
     158   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/MultiMPITest_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
     159    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     160   </view>
     161   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/MultiMPITest_translate.nlf" label="Post-Translate Simulation Model Report" >
     162    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     163   </view>
     164   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
     165   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="MultiMPITest_map.map" label="Map Log File" >
    166166    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    167167    <toc-item title="Design Information" target="Design Information" />
    … …  
    169169   </view>
    170170   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
    171    <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_preroute.twr" label="Post-Map Static Timing Report" >
     171   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_preroute.twr" label="Post-Map Static Timing Report" >
    172172    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    173173    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    … …  
    180180    <toc-item title="Trace Settings" target="Trace Settings:" />
    181181   </view>
    182    <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/CORE_MPI_map.nlf" label="Post-Map Simulation Model Report" />
    183    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_map.psr" label="Physical Synthesis Report" >
    184     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    185    </view>
    186    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="CORE_MPI_pad.txt" label="Pad Report" >
    187     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    188    </view>
    189    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="CORE_MPI.unroutes" label="Unroutes Report" >
    190     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    191    </view>
    192    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_preroute.tsi" label="Post-Map Constraints Interaction Report" >
    193     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    194    </view>
    195    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.grf" label="Guide Results Report" />
    196    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.dly" label="Asynchronous Delay Report" />
    197    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.clk_rgn" label="Clock Region Report" />
    198    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.tsi" label="Post-Place and Route Constraints Interaction Report" >
    199     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    200    </view>
    201    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
    202    <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/CORE_MPI_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
    203    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_sta.nlf" label="Primetime Netlist Report" >
    204     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    205    </view>
    206    <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.ibs" label="IBIS Model" >
     182   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/MultiMPITest_map.nlf" label="Post-Map Simulation Model Report" />
     183   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_map.psr" label="Physical Synthesis Report" >
     184    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     185   </view>
     186   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="MultiMPITest_pad.txt" label="Pad Report" >
     187    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     188   </view>
     189   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="MultiMPITest.unroutes" label="Unroutes Report" >
     190    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     191   </view>
     192   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_preroute.tsi" label="Post-Map Constraints Interaction Report" >
     193    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     194   </view>
     195   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.grf" label="Guide Results Report" />
     196   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.dly" label="Asynchronous Delay Report" />
     197   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.clk_rgn" label="Clock Region Report" />
     198   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.tsi" label="Post-Place and Route Constraints Interaction Report" >
     199    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     200   </view>
     201   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
     202   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/MultiMPITest_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
     203   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_sta.nlf" label="Primetime Netlist Report" >
     204    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     205   </view>
     206   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.ibs" label="IBIS Model" >
    207207    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
    208208    <toc-item title="Component" target="Component " />
    209209   </view>
    210    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.lck" label="Back-annotate Pin Report" >
     210   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.lck" label="Back-annotate Pin Report" >
    211211    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
    212212    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
    213213   </view>
    214    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.lpc" label="Locked Pin Constraints" >
     214   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.lpc" label="Locked Pin Constraints" >
    215215    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
    216216    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
    217217   </view>
    218    <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/CORE_MPI_timesim.nlf" label="Post-Fit Simulation Model Report" />
     218   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/MultiMPITest_timesim.nlf" label="Post-Fit Simulation Model Report" />
    219219   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
    220220   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
Note: See TracChangeset for help on using the changeset viewer.