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Changeset 75 for PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES
- Timestamp:
- Jan 15, 2014, 2:43:44 AM (11 years ago)
- Location:
- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03
- Files:
-
- 3 edited
-
FIFO_DP.vhd (modified) (1 diff)
-
OUTPUT_PORT_MODULE.vhd (modified) (2 diffs)
-
proto_send.vhd (modified) (5 diffs)
Legend:
- Unmodified
- Added
- Removed
-
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/FIFO_DP.vhd
r22 r75 41 41 full : out std_logic --set as '1' when the queue is full 42 42 ); 43 end fifo ;43 end fifo_dp; 44 44 45 45 architecture Behavioral of fifo_dp is -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/OUTPUT_PORT_MODULE.vhd
r69 r75 109 109 if rd_out_en='1' then 110 110 Et_out_fsm<=reading; 111 elsif tlimit= 350 then111 elsif tlimit=5000 then 112 112 Et_out_fsm<=dropping; 113 113 tlimit<=0; … … 131 131 sw<='0'; 132 132 Et_out_fsm<=Idle; 133 report "Attention Paquet perdu !à Output_Port_Module"; 133 134 n<=0; 134 135 end if; -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd
r71 r75 57 57 signal n,n_i:natural range 0 to 7; 58 58 signal wr_ok,rd_ok:std_logic:='0'; 59 signal sfifo_in,Data_to_send : std_logic_vector(Word-1 downto 0); 59 signal wr_ok_i,rd_ok_i:std_logic:='0'; 60 signal sfifo_in,Data_to_send,Data_to_send_i : std_logic_vector(Word-1 downto 0); 60 61 signal spush : std_logic:='0'; 61 62 signal err : std_logic_vector(Word-1 downto 0):=(others =>'0'); 62 63 begin 63 64 64 Fifo_copy_sync:process(clk )65 Fifo_copy_sync:process(clk,reset) 65 66 66 67 begin 67 if rising_edge(clk) then 68 68 69 69 70 if reset='1' then … … 71 72 Snd_state<=0; 72 73 P_len<=0; 74 Data_to_send<=(others=>'0'); 73 75 else 76 if rising_edge(clk) then 74 77 Snd_state<=Next_Snd_state; 75 78 n<=n_i; 76 79 p_len<=P_len_i; 80 Data_to_send<=Data_to_send_i; 81 wr_ok<=wr_ok_i; 82 rd_ok<=rd_ok_i; 77 83 end if; 78 84 end if; … … 81 87 Fifo_copy_val:process (Snd_state,Etsnd,copy_mode,data_to_send,rd_ok,wr_ok,spush) 82 88 begin 89 --fifo_out_wr_en<='0'; 90 --fifo_in_rd_en<='0'; 91 --fifo_out_data_in<=data_to_send; 83 92 if copy_mode='0' then 84 93 fifo_out_wr_en<=wr_ok; … … 95 104 -- process qui envoie des données en provenance d'un Fifo vers un Fifo 96 105 FIfo_to_fifo:process(snd_state,copy_mode,snd_start,snd_ack,fifo_in_empty, 97 fifo_out_full,Fifo_in_data_out,p_len )106 fifo_out_full,Fifo_in_data_out,p_len,n,mem,wr_ok,rd_ok) 98 107 variable onepop:std_logic:='0'; 99 108 begin 100 109 Next_snd_state<=snd_state; --valeur par defaut 110 Data_To_Send_i<=Data_to_send; 111 wr_ok_i<=wr_ok; 112 rd_ok_i<=rd_ok; 101 113 case snd_state is 102 114 … … 106 118 n_i<=0; 107 119 end if; 108 wr_ok <='0';rd_ok<='0';onepop:='0';120 wr_ok_i<='0';rd_ok_i<='0';onepop:='0'; 109 121 snd_comp<='0'; 110 when 1=> if P_len>0 then122 when 1=> --placer la première donnée sur le bus 111 123 if copy_mode='1' then 112 if fifo_in_empty='0' and onepop='0' then 113 data_to_send <=fifo_in_data_out ; 114 rd_Ok<='1'; 115 onepop:=not onepop; --une donnée lue il faut arrêter de dépiler 116 124 if fifo_in_empty='0' then 125 data_to_send_i <=fifo_in_data_out ; 126 end if; 117 127 else 118 rd_Ok<='0'; 119 end if; 128 data_to_send_i<=mem(n); 129 end if; 130 next_snd_state<=2; 131 when 2=> if P_len>0 then 132 if copy_mode='1' then 133 if fifo_in_empty='0' and onepop='0' then 134 data_to_send_i <=fifo_in_data_out ; 135 rd_Ok_i<='1'; 136 onepop:='1'; --une donnée lue il faut arrêter de dépiler 137 138 else 139 rd_Ok_i<='0'; 140 end if; 120 141 else 121 onepop:='1'; 122 data_to_send <=mem(n);142 onepop:='1';rd_ok_i<='0'; --pas besoin de signal de lecture ici 143 data_to_send_i<=mem(n); 123 144 end if; 124 145 125 if (fifo_out_full = '0') and onepop='1' then wr_ok<='1'; 126 onepop:=not onepop; 127 wr_ok<='1'; 128 p_len_i<=p_len-1; 129 n_i<=n+1; 130 146 if (fifo_out_full = '0') and onepop='1' then 147 wr_ok_i<='1'; 148 onepop:='0'; 149 p_len_i<=p_len-1; 150 n_i<=n+1; 131 151 else 132 wr_Ok<='0'; 133 152 wr_Ok_i<='0'; 134 153 end if; 135 154 else 136 rd_ok<='0';wr_ok<='0'; 137 next_snd_state<=2; 155 rd_ok_i<='0'; 156 wr_ok_i<='0'; 157 next_snd_state<=3; 138 158 snd_comp<='1'; 139 159 end if; 140 when 2=> --fin de la copie160 when 3 => --fin de la copie 141 161 if snd_ack='1' then 142 162 143 next_snd_state<= 3;163 next_snd_state<=4; 144 164 end if; 145 wr_ok <='0';rd_ok<='0';165 wr_ok_i<='0';rd_ok_i<='0'; 146 166 snd_comp<='1'; 147 data_to_send <=(others=>'-');148 when 3=>next_snd_state<=0;167 168 when 4 =>next_snd_state<=0; 149 169 snd_comp<='0'; 150 170 151 171 when others => next_snd_state<=0; 152 172 snd_comp<='0'; 153 rd_ok <='0';154 wr_ok <='0';155 data_to_send <=(others=>'-');173 rd_ok_i<='0'; 174 wr_ok_i<='0'; 175 data_to_send_i <=(others=>'U'); 156 176 end case; 157 177 end process FIfo_to_fifo;
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