Changeset 88 for PROJECT_SMART_EEG
- Timestamp:
- Mar 3, 2014, 4:09:09 PM (11 years ago)
- File:
-
- 1 edited
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PROJECT_SMART_EEG/trunk/hw/projects/sync_sys/qsys.qsys
r86 r88 50 50 } 51 51 } 52 element stream_merger_0.ctrl 53 { 54 datum baseAddress 55 { 56 value = "139264"; 57 type = "String"; 58 } 59 } 60 element video_codec_0.ctrl 61 { 62 datum baseAddress 63 { 64 value = "140288"; 65 type = "String"; 66 } 67 } 52 68 element synchro_0.ctrl 53 69 { … … 58 74 } 59 75 } 60 element stream_merger_0.ctrl61 { 62 datum baseAddress 63 { 64 value = "1 39264";76 element frame_grabber_0.ctrl 77 { 78 datum baseAddress 79 { 80 value = "141312"; 65 81 type = "String"; 66 82 } … … 79 95 { 80 96 value = "137216"; 81 type = "String";82 }83 }84 element video_codec_0.ctrl85 {86 datum baseAddress87 {88 value = "140288";89 type = "String";90 }91 }92 element frame_grabber_0.ctrl93 {94 datum baseAddress95 {96 value = "141312";97 97 type = "String"; 98 98 } … … 203 203 <parameter name="hdlLanguage" value="VERILOG" /> 204 204 <parameter name="maxAdditionalLatency" value="1" /> 205 <parameter name="projectName" value=" smartEEG_v1.qpf" />205 <parameter name="projectName" value="" /> 206 206 <parameter name="sopcBorderPoints" value="false" /> 207 207 <parameter name="systemHash" value="0" />
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