Changeset 89 for PROJECT_SMART_EEG


Ignore:
Timestamp:
Mar 3, 2014, 4:47:59 PM (11 years ago)
Author:
szahmed
Message:

Added Headline comments for Verilog files explaining their brief properties, version number etc.

Location:
PROJECT_SMART_EEG/trunk/hw/sync_sys
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec/audio_codec.v

    r84 r89  
    1 // audio_codec.v
    2 
    3 // This file was auto-generated as a prototype implementation of a module
    4 // created in component editor.  It ties off all outputs to ground and
    5 // ignores all inputs.  It needs to be edited to make it do something
    6 // useful.
    7 //
    8 // This file will not be automatically regenerated.  You should check it in
    9 // to your version control system if you want to keep it.
     1/********************************************************************
     2 *                    COPYRIGHT LIP6 2014
     3 *-----------------------------------------------------------------*/
     4/**
     5 * @file    audio_codec.v
     6 * @brief   Performs Audio Compression
     7 *
     8 * This module perfoms audio compression of raw data received from AvalonST sink and sends
     9 * the compressed audio via AvalonST source to stream merger module
     10 *
     11 * @author  S. Z. Ahmed         <syed-zahid.ahmed@lip6.fr>
     12 * @author  L. Lambert          <laurent.lambert@lip6.fr>
     13 * @date    Fri. 28 Feb. 2014
     14 *
     15 * Revision History
     16 * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
     17 *
     18 *******************************************************************/
    1019
    1120`timescale 1 ps / 1 ps

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec/exg_codec.v

    r84 r89  
    1 // exg_codec.v
    2 
    3 // This file was auto-generated as a prototype implementation of a module
    4 // created in component editor.  It ties off all outputs to ground and
    5 // ignores all inputs.  It needs to be edited to make it do something
    6 // useful.
    7 //
    8 // This file will not be automatically regenerated.  You should check it in
    9 // to your version control system if you want to keep it.
     1/********************************************************************
     2 *                    COPYRIGHT LIP6 2014
     3 *-----------------------------------------------------------------*/
     4/**
     5 * @file    exg_codec.v
     6 * @brief   Performs EXG data Compression/Processing
     7 *
     8 * This module perfoms recieves raw EXG data from AvalonST sink, perfoms compression/processing of the data
     9 * and sends the input raw data and compressed data to stream merger module via AvalonST sources
     10 *
     11 * @author  S. Z. Ahmed         <syed-zahid.ahmed@lip6.fr>
     12 * @author  L. Lambert          <laurent.lambert@lip6.fr>
     13 * @date    Fri. 28 Feb. 2014
     14 *
     15 * Revision History
     16 * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
     17 *
     18 *******************************************************************/
    1019
    1120`timescale 1 ps / 1 ps

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber/frame_grabber.v

    r84 r89  
    1 // frame_grabber.v
    2 
    3 // This file was auto-generated as a prototype implementation of a module
    4 // created in component editor.  It ties off all outputs to ground and
    5 // ignores all inputs.  It needs to be edited to make it do something
    6 // useful.
    7 //
    8 // This file will not be automatically regenerated.  You should check it in
    9 // to your version control system if you want to keep it.
     1/********************************************************************
     2 *                    COPYRIGHT LIP6 2014
     3 *-----------------------------------------------------------------*/
     4/**
     5 * @file    frame_grabber.v
     6 * @brief   Performs frame grabbing, Bayer->RGB conversion and sends the raw data to video codec module
     7 *
     8 * This module perfoms the frame grabbing of the terasic D5M camera that is connected with GPIO of DE4, it then
     9 * performs Bayer->RGB conversion and sends the raw data to the video codec via AvalonST source
     10 *
     11 * @author  S. Z. Ahmed         <syed-zahid.ahmed@lip6.fr>
     12 * @author  L. Lambert          <laurent.lambert@lip6.fr>
     13 * @date    Fri. 28 Feb. 2014
     14 *
     15 * Revision History
     16 * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
     17 *
     18 *******************************************************************/
    1019
    1120`timescale 1 ps / 1 ps
    … …  
    1322                input  wire        clk,                //     clock.clk
    1423                input  wire        reset,              //     reset.reset
    15                 input  wire [7:0]  avs_s0_address,     //      ctrl.address
    16                 input  wire        avs_s0_read,        //          .read
    17                 output wire [31:0] avs_s0_readdata,    //          .readdata
    18                 input  wire        avs_s0_write,       //          .write
    19                 input  wire [31:0] avs_s0_writedata,   //          .writedata
    20                 output wire        avs_s0_waitrequest, //          .waitrequest
    21                 output wire [31:0] aso_out0_data,      // raw_video.data
    22                 input  wire        aso_out0_ready,     //          .ready
    23                 output wire        aso_out0_valid,      //          .valid
     24                input  wire [7:0]  avs_ctrl_address,     //      ctrl.address
     25                input  wire        avs_ctrl_read,        //          .read
     26                output wire [31:0] avs_ctrl_readdata,    //          .readdata
     27                input  wire        avs_ctrl_write,       //          .write
     28                input  wire [31:0] avs_ctrl_writedata,   //          .writedata
     29                output wire        avs_ctrl_waitrequest, //          .waitrequest
     30                output wire [31:0] aso_raw_video_data,      // raw_video.data
     31                input  wire        aso_raw_video_ready,     //          .ready
     32                output wire        aso_raw_video_valid,      //          .valid
    2433               
    2534                input               [11:0]              D5M_D,
    … …  
    3746        // TODO: Auto-generated HDL template
    3847
    39         assign avs_s0_waitrequest = 1'b0;
     48        assign avs_ctrl_waitrequest = 1'b0;
    4049
    41         assign avs_s0_readdata = 32'b00000000000000000000000000000000;
     50        assign avs_ctrl_readdata = 32'b00000000000000000000000000000000;
    4251
    4352        assign aso_out0_valid = 1'b0;

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber/signal_grabber.v

    r84 r89  
    1 // signal_grabber.v
    2 
    3 // This file was auto-generated as a prototype implementation of a module
    4 // created in component editor.  It ties off all outputs to ground and
    5 // ignores all inputs.  It needs to be edited to make it do something
    6 // useful.
    7 //
    8 // This file will not be automatically regenerated.  You should check it in
    9 // to your version control system if you want to keep it.
     1/********************************************************************
     2 *                    COPYRIGHT LIP6 2014
     3 *-----------------------------------------------------------------*/
     4/**
     5 * @file    signal_grabber.v
     6 * @brief   Performs signal grabbing of EXG and Audio data coming from ETIS
     7 *
     8 * This module performs grabbing of time-stamped EXG and Audio data coming from ETIS (In initial versions create dummy/test data via internal logic of
     9 * this module for validation of rest of the system). It sends the data received/Modeled from/of ETIS to Audio and EXG coders via AvalonST source
     10 *
     11 * @author  S. Z. Ahmed         <syed-zahid.ahmed@lip6.fr>
     12 * @author  L. Lambert          <laurent.lambert@lip6.fr>
     13 * @date    Fri. 28 Feb. 2014
     14 *
     15 * Revision History
     16 * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
     17 *
     18 *******************************************************************/
    1019
    1120`timescale 1 ps / 1 ps

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger/stream_merger.v

    r84 r89  
    1 // stream_merger.v
    2 
    3 // This file was auto-generated as a prototype implementation of a module
    4 // created in component editor.  It ties off all outputs to ground and
    5 // ignores all inputs.  It needs to be edited to make it do something
    6 // useful.
    7 //
    8 // This file will not be automatically regenerated.  You should check it in
    9 // to your version control system if you want to keep it.
     1/********************************************************************
     2 *                    COPYRIGHT LIP6 2014
     3 *-----------------------------------------------------------------*/
     4/**
     5 * @file    stream_merger.v
     6 * @brief   Receives time-stamped {Downscaled RAW Video, Compressed Video, Raw EXG, Compressed EXG, Compressed Audio)
     7 *          and sends them to tramission Card (exptected to be via HSMC)
     8 *
     9 * This module receives three components of SmartEEG data.
     10 * 1- Time-stamped downscaled RAW (for live privew) and Compressed Video from the Video coder via AvalonST sinks.
     11 * 2- Time stamped compressed Audio via AvalonST sink
     12 * 3- Time stamped RAW and Compressed EXG data via AvalonST sinks
     13 * It transmits these data channels to transmitter card (ARM-based CycloneV FPGA SocKit board connected via HSMC)
     14 *
     15 * @author  S. Z. Ahmed         <syed-zahid.ahmed@lip6.fr>
     16 * @author  L. Lambert          <laurent.lambert@lip6.fr>
     17 * @date    Fri. 28 Feb. 2014
     18 *
     19 * Revision History
     20 * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
     21 *
     22 *******************************************************************/
    1023
    1124`timescale 1 ps / 1 ps

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro/synchro.v

    r84 r89  
    1 // synchro.v
    2 
    3 // This file was auto-generated as a prototype implementation of a module
    4 // created in component editor.  It ties off all outputs to ground and
    5 // ignores all inputs.  It needs to be edited to make it do something
    6 // useful.
    7 //
    8 // This file will not be automatically regenerated.  You should check it in
    9 // to your version control system if you want to keep it.
     1/********************************************************************
     2 *                    COPYRIGHT LIP6 2014
     3 *-----------------------------------------------------------------*/
     4/**
     5 * @file    synchro.v
     6 * @brief   Creats video trigger, time-stamp/sync clock and rest signal (for ETIS)
     7 *
     8 * This module generates the Video trigger signal for the Camera at the choosen fps. It also generates the time-stamp/sync clock that is
     9 * used by both Acquision (ETIS) and Compression (Lip6) boards for time-stamp counters along with a start signal whic resets the time-stamp
     10 * counters when the acquisition start command comes from PC (Acacia). The value of time-stamp register is transmitted to the Video coder via AvalonST source
     11 *
     12 * @author  S. Z. Ahmed         <syed-zahid.ahmed@lip6.fr>
     13 * @author  L. Lambert          <laurent.lambert@lip6.fr>
     14 * @date    Fri. 28 Feb. 2014
     15 *
     16 * Revision History
     17 * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
     18 *
     19 *******************************************************************/
    1020
    1121`timescale 1 ps / 1 ps
    1222module synchro (
    13                 input  wire [7:0]  avs_s0_address,        //           s0.address
    14                 input  wire        avs_s0_read,           //             .read
    15                 output wire [31:0] avs_s0_readdata,       //             .readdata
    16                 input  wire        avs_s0_write,          //             .write
    17                 input  wire [31:0] avs_s0_writedata,      //             .writedata
    18                 output wire        avs_s0_waitrequest,    //             .waitrequest
     23                input  wire [7:0]  avs_ctrl_address,        //           ctrl.address
     24                input  wire        avs_ctrl_read,           //             .read
     25                output wire [31:0] avs_ctrl_readdata,       //             .readdata
     26                input  wire        avs_ctrl_write,          //             .write
     27                input  wire [31:0] avs_ctrl_writedata,      //             .writedata
     28                output wire        avs_ctrl_waitrequest,    //             .waitrequest
    1929                input  wire        clk,                   //        clock.clk
    2030                input  wire        reset,                 //        reset.reset
    … …  
    2939        // TODO: Auto-generated HDL template
    3040
    31         assign avs_s0_waitrequest = 1'b0;
     41        assign avs_ctrl_waitrequest = 1'b0;
    3242
    33         assign avs_s0_readdata = 32'b00000000000000000000000000000000;
     43        assign avs_ctrl_readdata = 32'b00000000000000000000000000000000;
    3444
    3545        assign video_trigger = 1'b0;

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec/video_codec.v

    r84 r89  
    1 // video_codec.v
    2 
    3 // This file was auto-generated as a prototype implementation of a module
    4 // created in component editor.  It ties off all outputs to ground and
    5 // ignores all inputs.  It needs to be edited to make it do something
    6 // useful.
    7 //
    8 // This file will not be automatically regenerated.  You should check it in
    9 // to your version control system if you want to keep it.
     1/********************************************************************
     2 *                    COPYRIGHT LIP6 2014
     3 *-----------------------------------------------------------------*/
     4/**
     5 * @file    video_codec.v
     6 * @brief   Performs Video Compression and Downscaled raw video bypass
     7 *
     8 * This module receives the RAW video data from Frame Grabber via AvalonST sink. It performs Video Compression and Downscaled RAW video bypass (for live preview),
     9 * it adds time-stamp to the video frames that is received via AvalonST sink from synchro module. It transmitts the RAW and Compressed Data to stream merger via AvalonST sources
     10 *
     11 * @author  S. Z. Ahmed         <syed-zahid.ahmed@lip6.fr>
     12 * @author  L. Lambert          <laurent.lambert@lip6.fr>
     13 * @date    Fri. 28 Feb. 2014
     14 *
     15 * Revision History
     16 * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
     17 *
     18 *******************************************************************/
    1019
    1120`timescale 1 ps / 1 ps
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