Changeset 89 for PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger

Timestamp:

Mar 3, 2014, 4:47:59 PM (11 years ago)

Author:

szahmed

Message:

Added Headline comments for Verilog files explaining their brief properties, version number etc.

File:

• PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger/stream_merger.v (modified) (1 diff)

PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger/stream_merger.v

@@ -1 @@
-// stream_merger.v
-
-// This file was auto-generated as a prototype implementation of a module
-// created in component editor.  It ties off all outputs to ground and
-// ignores all inputs.  It needs to be edited to make it do something
-// useful.
-// 
-// This file will not be automatically regenerated.  You should check it in
-// to your version control system if you want to keep it.
+/********************************************************************
+ *                    COPYRIGHT LIP6 2014
+ *-----------------------------------------------------------------*/
+/** 
+ * @file    stream_merger.v
+ * @brief   Receives time-stamped {Downscaled RAW Video, Compressed Video, Raw EXG, Compressed EXG, Compressed Audio)
+ *          and sends them to tramission Card (exptected to be via HSMC)
+ *
+ * This module receives three components of SmartEEG data.
+ * 1- Time-stamped downscaled RAW (for live privew) and Compressed Video from the Video coder via AvalonST sinks.
+ * 2- Time stamped compressed Audio via AvalonST sink
+ * 3- Time stamped RAW and Compressed EXG data via AvalonST sinks
+ * It transmits these data channels to transmitter card (ARM-based CycloneV FPGA SocKit board connected via HSMC)
+ *
+ * @author  S. Z. Ahmed         <syed-zahid.ahmed@lip6.fr>
+ * @author  L. Lambert          <laurent.lambert@lip6.fr>
+ * @date    Fri. 28 Feb. 2014
+ * 
+ * Revision History
+ * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
+ *
+ *******************************************************************/
 
 `timescale 1 ps / 1 ps