Changeset 87 for PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger

Timestamp:

Mar 3, 2014, 4:09:09 PM (11 years ago)

Author:

lambert

Message:

Adding generation simulation support for verilog

File:

• PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger/stream_merger_hw.tcl (modified) (4 diffs)

PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger/stream_merger_hw.tcl

@@ -1 +1 @@
 # TCL File Generated by Component Editor 13.1
-# Fri Feb 28 18:03:07 CET 2014
+# Mon Mar 03 15:30:43 CET 2014
 # DO NOT MODIFY
 
@@ -6 +6 @@
 # 
 # stream_merger "stream_merger" v1.0
-#  2014.02.28.18:03:07
+#  2014.03.03.15:30:43
 # 
 # 
@@ -41 +41 @@
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 add_fileset_file stream_merger.v VERILOG PATH stream_merger.v TOP_LEVEL_FILE
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG TOP_LEVEL stream_merger
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file stream_merger.v VERILOG PATH stream_merger.v
 
 
@@ -107 +112 @@
 set_interface_property ctrl SVD_ADDRESS_GROUP ""
 
-add_interface_port ctrl avs_s0_address address Input 8
-add_interface_port ctrl avs_s0_read read Input 1
-add_interface_port ctrl avs_s0_readdata readdata Output 32
-add_interface_port ctrl avs_s0_write write Input 1
-add_interface_port ctrl avs_s0_writedata writedata Input 32
-add_interface_port ctrl avs_s0_waitrequest waitrequest Output 1
+add_interface_port ctrl avs_ctrl_address address Input 8
+add_interface_port ctrl avs_ctrl_read read Input 1
+add_interface_port ctrl avs_ctrl_readdata readdata Output 32
+add_interface_port ctrl avs_ctrl_write write Input 1
+add_interface_port ctrl avs_ctrl_writedata writedata Input 32
+add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1
 set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
 set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0