Changeset 89 for PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec

Timestamp:

Mar 3, 2014, 4:47:59 PM (11 years ago)

Author:

szahmed

Message:

Added Headline comments for Verilog files explaining their brief properties, version number etc.

File:

• PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec/video_codec.v (modified) (1 diff)

PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec/video_codec.v

@@ -1 @@
-// video_codec.v
-
-// This file was auto-generated as a prototype implementation of a module
-// created in component editor.  It ties off all outputs to ground and
-// ignores all inputs.  It needs to be edited to make it do something
-// useful.
-// 
-// This file will not be automatically regenerated.  You should check it in
-// to your version control system if you want to keep it.
+/********************************************************************
+ *                    COPYRIGHT LIP6 2014
+ *-----------------------------------------------------------------*/
+/** 
+ * @file    video_codec.v
+ * @brief   Performs Video Compression and Downscaled raw video bypass
+ *
+ * This module receives the RAW video data from Frame Grabber via AvalonST sink. It performs Video Compression and Downscaled RAW video bypass (for live preview),
+ * it adds time-stamp to the video frames that is received via AvalonST sink from synchro module. It transmitts the RAW and Compressed Data to stream merger via AvalonST sources
+ *
+ * @author  S. Z. Ahmed         <syed-zahid.ahmed@lip6.fr>
+ * @author  L. Lambert          <laurent.lambert@lip6.fr>
+ * @date    Fri. 28 Feb. 2014
+ * 
+ * Revision History
+ * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
+ *
+ *******************************************************************/
 
 `timescale 1 ps / 1 ps