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source:
PROJECT_SMART_EEG
/
trunk
/
hw
/
sync_sys
/
exg_codec
/
exg_codec.v
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Rev
Age
Author
Log Message
(edit)
@89
11 years
szahmed
Added Headline comments for Verilog files explaining their brief …
(copy)
@84
11 years
lambert
Adding hierarchical subdirectory for every component
copied from
PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec.v
:
(add)
@83
11 years
szahmed
Initial Commit
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