| 1 | #include <systemc.h> |
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| 2 | |
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| 3 | #define ASSERT(x) \ |
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| 4 | { \ |
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| 5 | if (!(x)) \ |
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| 6 | { \ |
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| 7 | cerr << "ASSERT : " #x "\n"; \ |
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| 8 | exit (1); \ |
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| 9 | } \ |
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| 10 | } |
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| 11 | |
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| 12 | using namespace std; |
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| 13 | |
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| 14 | struct test : sc_module { |
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| 15 | int32_t reg; |
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| 16 | sc_signal<bool> reg_bool; |
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| 17 | sc_signal<int> reg_int; |
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| 18 | sc_signal<unsigned int> reg_unsigned_int; |
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| 19 | sc_signal<char> reg_char; |
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| 20 | sc_signal<double> reg_double; |
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| 21 | sc_signal<long> reg_long; |
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| 22 | sc_signal<sc_uint<32> > reg_ui32; |
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| 23 | sc_signal<sc_uint<16> > reg_ui16; |
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| 24 | sc_signal<sc_uint<6> > reg_ui6; |
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| 25 | sc_signal<sc_int<32> > reg_i32; |
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| 26 | sc_signal<sc_int<16> > reg_i16; |
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| 27 | sc_signal<sc_int<6> > reg_i6; |
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| 28 | |
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| 29 | sc_in_clk clk; |
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| 30 | sc_in<bool> resetn; |
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| 31 | |
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| 32 | void trans () |
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| 33 | { |
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| 34 | if (resetn.read() == true) |
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| 35 | { |
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| 36 | ASSERT(((reg & 1)) == reg_bool .read()); |
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| 37 | ASSERT(((int) reg) == reg_int .read()); |
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| 38 | ASSERT(((unsigned int)reg) == reg_unsigned_int .read()); |
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| 39 | ASSERT(((char) reg) == reg_char .read()); |
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| 40 | #if 0 |
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| 41 | cout << (double)reg << " " << reg_double.read() << endl; |
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| 42 | cout << sizeof (double) << " " << sizeof (reg_double.read()) << endl; |
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| 43 | #endif |
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| 44 | ASSERT(((double)reg) == reg_double.read()); |
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| 45 | ASSERT(((long) reg) == reg_long .read()); |
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| 46 | ASSERT(((unsigned int) reg & 0xFFFFFFFF) == (unsigned int) (reg_ui32 .read())); |
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| 47 | ASSERT(((unsigned int) reg & 0x0000FFFF) == (unsigned int) (reg_ui16 .read())); |
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| 48 | #if 0 |
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| 49 | cerr << reg_ui6.read() << " " << (reg & 0x0000003F) << endl; |
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| 50 | #endif |
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| 51 | ASSERT(((unsigned int) reg & 0x0000003F) == (unsigned int) (reg_ui6 .read())); |
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| 52 | ASSERT(((signed int) reg & 0xFFFFFFFF) == (signed int) (reg_i32 .read())); |
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| 53 | ASSERT(((signed int) reg & 0x0000FFFF) == (signed int) (reg_i16 .read())); |
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| 54 | ASSERT(((signed int) reg & 0x0000003F) == (signed int) (reg_i6 .read())); |
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| 55 | reg = reg + 1; |
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| 56 | reg_bool = reg & 1; |
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| 57 | reg_int = reg; |
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| 58 | reg_unsigned_int = reg; |
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| 59 | reg_char = reg; |
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| 60 | reg_double .write(reg); |
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| 61 | reg_long = reg; |
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| 62 | reg_ui32 = reg; |
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| 63 | reg_ui16 = reg; |
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| 64 | reg_ui6 = reg; |
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| 65 | reg_i32 = reg; |
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| 66 | reg_i16 = reg; |
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| 67 | reg_i6 = reg; |
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| 68 | } else { |
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| 69 | reg = 0; |
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| 70 | reg_bool = 0; |
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| 71 | reg_int = 0; |
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| 72 | reg_unsigned_int = 0; |
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| 73 | reg_char = 0; |
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| 74 | reg_double = 0; |
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| 75 | reg_long = 0; |
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| 76 | reg_ui32 = 0; |
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| 77 | reg_ui16 = 0; |
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| 78 | reg_ui6 = 0; |
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| 79 | reg_i32 = 0; |
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| 80 | reg_i16 = 0; |
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| 81 | reg_i6 = 0; |
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| 82 | } |
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| 83 | } |
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| 84 | |
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| 85 | SC_HAS_PROCESS(test); |
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| 86 | test (sc_module_name n) : sc_module (n), |
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| 87 | clk("clk") |
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| 88 | { |
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| 89 | SC_METHOD(trans); |
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| 90 | sensitive << clk.pos(); |
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| 91 | dont_initialize(); |
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| 92 | }; |
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| 93 | }; |
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| 94 | |
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| 95 | int sc_main (int argc, char *argv[]) |
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| 96 | { |
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| 97 | sc_clock signal_clk("my_clock",1, 0.5); |
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| 98 | sc_signal<bool> resetn("resetn"); |
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| 99 | |
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| 100 | test test1("test1"); |
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| 101 | test1.clk (signal_clk); |
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| 102 | test1.resetn (resetn); |
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| 103 | |
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| 104 | // Init & run |
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| 105 | sc_start (0); |
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| 106 | |
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| 107 | resetn = false; |
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| 108 | sc_start (4); |
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| 109 | resetn = true; |
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| 110 | sc_start (100); |
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| 111 | |
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| 112 | return EXIT_SUCCESS; |
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| 113 | } |
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| 114 | |
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| 115 | #undef sc_inout |
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