[331] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_mem_cache.h |
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| 3 | * Date : 26/10/2008 |
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| 4 | * Copyright : UPMC / LIP6 |
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| 5 | * Authors : Alain Greiner / Eric Guthmuller |
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| 6 | * |
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| 7 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 8 | * |
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| 9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 10 | * |
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| 11 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 12 | * under the terms of the GNU Lesser General Public License as published |
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| 13 | * by the Free Software Foundation; version 2.1 of the License. |
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| 14 | * |
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| 15 | * SoCLib is distributed in the hope that it will be useful, but |
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| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | * Lesser General Public License for more details. |
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| 19 | * |
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| 20 | * You should have received a copy of the GNU Lesser General Public |
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| 21 | * License along with SoCLib; if not, write to the Free Software |
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| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 23 | * 02110-1301 USA |
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| 24 | * |
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| 25 | * SOCLIB_LGPL_HEADER_END |
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| 26 | * |
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[495] | 27 | * Maintainers: alain.greiner@lip6.fr |
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| 28 | * eric.guthmuller@polytechnique.edu |
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[331] | 29 | * cesar.fuguet-tortolero@lip6.fr |
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| 30 | * alexandre.joannou@lip6.fr |
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| 31 | */ |
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| 32 | |
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| 33 | #ifndef SOCLIB_CABA_MEM_CACHE_H |
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| 34 | #define SOCLIB_CABA_MEM_CACHE_H |
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| 35 | |
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| 36 | #include <inttypes.h> |
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| 37 | #include <systemc> |
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| 38 | #include <list> |
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| 39 | #include <cassert> |
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| 40 | #include "arithmetics.h" |
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| 41 | #include "alloc_elems.h" |
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| 42 | #include "caba_base_module.h" |
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| 43 | #include "vci_target.h" |
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| 44 | #include "vci_initiator.h" |
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| 45 | #include "generic_fifo.h" |
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| 46 | #include "mapping_table.h" |
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| 47 | #include "int_tab.h" |
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| 48 | #include "generic_llsc_global_table.h" |
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| 49 | #include "mem_cache_directory.h" |
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| 50 | #include "xram_transaction.h" |
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| 51 | #include "update_tab.h" |
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| 52 | #include "dspin_interface.h" |
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[771] | 53 | #include "dspin_rwt_param.h" |
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[331] | 54 | |
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[395] | 55 | #define TRT_ENTRIES 4 // Number of entries in TRT |
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| 56 | #define UPT_ENTRIES 4 // Number of entries in UPT |
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[468] | 57 | #define IVT_ENTRIES 4 // Number of entries in IVT |
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[395] | 58 | #define HEAP_ENTRIES 1024 // Number of entries in HEAP |
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[331] | 59 | |
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| 60 | namespace soclib { namespace caba { |
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[395] | 61 | |
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[331] | 62 | using namespace sc_core; |
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| 63 | |
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[385] | 64 | template<typename vci_param_int, |
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| 65 | typename vci_param_ext, |
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| 66 | size_t dspin_in_width, |
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| 67 | size_t dspin_out_width> |
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[331] | 68 | class VciMemCache |
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| 69 | : public soclib::caba::BaseModule |
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| 70 | { |
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[385] | 71 | typedef typename vci_param_int::fast_addr_t addr_t; |
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| 72 | typedef typename sc_dt::sc_uint<64> wide_data_t; |
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[449] | 73 | typedef uint32_t data_t; |
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| 74 | typedef uint32_t tag_t; |
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| 75 | typedef uint32_t be_t; |
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| 76 | typedef uint32_t copy_t; |
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[385] | 77 | |
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[331] | 78 | /* States of the TGT_CMD fsm */ |
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[434] | 79 | enum tgt_cmd_fsm_state_e |
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| 80 | { |
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[331] | 81 | TGT_CMD_IDLE, |
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| 82 | TGT_CMD_READ, |
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| 83 | TGT_CMD_WRITE, |
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[434] | 84 | TGT_CMD_CAS, |
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[767] | 85 | TGT_CMD_CONFIG, |
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| 86 | TGT_CMD_ERROR |
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[331] | 87 | }; |
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| 88 | |
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| 89 | /* States of the TGT_RSP fsm */ |
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[395] | 90 | enum tgt_rsp_fsm_state_e |
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| 91 | { |
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[331] | 92 | TGT_RSP_READ_IDLE, |
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| 93 | TGT_RSP_WRITE_IDLE, |
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| 94 | TGT_RSP_CAS_IDLE, |
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| 95 | TGT_RSP_XRAM_IDLE, |
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[430] | 96 | TGT_RSP_MULTI_ACK_IDLE, |
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[331] | 97 | TGT_RSP_CLEANUP_IDLE, |
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[767] | 98 | TGT_RSP_TGT_CMD_IDLE, |
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[545] | 99 | TGT_RSP_CONFIG_IDLE, |
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[331] | 100 | TGT_RSP_READ, |
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| 101 | TGT_RSP_WRITE, |
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| 102 | TGT_RSP_CAS, |
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| 103 | TGT_RSP_XRAM, |
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[430] | 104 | TGT_RSP_MULTI_ACK, |
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[545] | 105 | TGT_RSP_CLEANUP, |
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[767] | 106 | TGT_RSP_TGT_CMD, |
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| 107 | TGT_RSP_CONFIG |
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[331] | 108 | }; |
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| 109 | |
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| 110 | /* States of the DSPIN_TGT fsm */ |
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[395] | 111 | enum cc_receive_fsm_state_e |
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| 112 | { |
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[331] | 113 | CC_RECEIVE_IDLE, |
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| 114 | CC_RECEIVE_CLEANUP, |
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[403] | 115 | CC_RECEIVE_CLEANUP_EOP, |
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[331] | 116 | CC_RECEIVE_MULTI_ACK |
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| 117 | }; |
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| 118 | |
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| 119 | /* States of the CC_SEND fsm */ |
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[395] | 120 | enum cc_send_fsm_state_e |
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| 121 | { |
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[331] | 122 | CC_SEND_XRAM_RSP_IDLE, |
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| 123 | CC_SEND_WRITE_IDLE, |
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[767] | 124 | CC_SEND_READ_IDLE, |
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[331] | 125 | CC_SEND_CAS_IDLE, |
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[545] | 126 | CC_SEND_CONFIG_IDLE, |
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[331] | 127 | CC_SEND_XRAM_RSP_BRDCAST_HEADER, |
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| 128 | CC_SEND_XRAM_RSP_BRDCAST_NLINE, |
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| 129 | CC_SEND_XRAM_RSP_INVAL_HEADER, |
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| 130 | CC_SEND_XRAM_RSP_INVAL_NLINE, |
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[477] | 131 | CC_SEND_READ_NCC_INVAL_HEADER, |
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| 132 | CC_SEND_READ_NCC_INVAL_NLINE, |
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| 133 | CC_SEND_WRITE_NCC_INVAL_HEADER, |
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| 134 | CC_SEND_WRITE_NCC_INVAL_NLINE, |
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[331] | 135 | CC_SEND_WRITE_BRDCAST_HEADER, |
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| 136 | CC_SEND_WRITE_BRDCAST_NLINE, |
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| 137 | CC_SEND_WRITE_UPDT_HEADER, |
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| 138 | CC_SEND_WRITE_UPDT_NLINE, |
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| 139 | CC_SEND_WRITE_UPDT_DATA, |
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| 140 | CC_SEND_CAS_BRDCAST_HEADER, |
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| 141 | CC_SEND_CAS_BRDCAST_NLINE, |
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| 142 | CC_SEND_CAS_UPDT_HEADER, |
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| 143 | CC_SEND_CAS_UPDT_NLINE, |
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| 144 | CC_SEND_CAS_UPDT_DATA, |
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[545] | 145 | CC_SEND_CAS_UPDT_DATA_HIGH, |
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| 146 | CC_SEND_CONFIG_INVAL_HEADER, |
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| 147 | CC_SEND_CONFIG_INVAL_NLINE, |
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| 148 | CC_SEND_CONFIG_BRDCAST_HEADER, |
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| 149 | CC_SEND_CONFIG_BRDCAST_NLINE |
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[331] | 150 | }; |
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| 151 | |
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| 152 | /* States of the MULTI_ACK fsm */ |
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[395] | 153 | enum multi_ack_fsm_state_e |
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| 154 | { |
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[331] | 155 | MULTI_ACK_IDLE, |
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| 156 | MULTI_ACK_UPT_LOCK, |
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| 157 | MULTI_ACK_UPT_CLEAR, |
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[495] | 158 | MULTI_ACK_WRITE_RSP |
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[331] | 159 | }; |
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| 160 | |
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[434] | 161 | /* States of the CONFIG fsm */ |
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| 162 | enum config_fsm_state_e |
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| 163 | { |
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| 164 | CONFIG_IDLE, |
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| 165 | CONFIG_LOOP, |
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[495] | 166 | CONFIG_WAIT, |
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[434] | 167 | CONFIG_RSP, |
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| 168 | CONFIG_DIR_REQ, |
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| 169 | CONFIG_DIR_ACCESS, |
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[495] | 170 | CONFIG_IVT_LOCK, |
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[434] | 171 | CONFIG_BC_SEND, |
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[495] | 172 | CONFIG_INVAL_SEND, |
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[439] | 173 | CONFIG_HEAP_REQ, |
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| 174 | CONFIG_HEAP_SCAN, |
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| 175 | CONFIG_HEAP_LAST, |
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[495] | 176 | CONFIG_TRT_LOCK, |
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| 177 | CONFIG_TRT_SET, |
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| 178 | CONFIG_PUT_REQ |
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[434] | 179 | }; |
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| 180 | |
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[331] | 181 | /* States of the READ fsm */ |
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[395] | 182 | enum read_fsm_state_e |
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| 183 | { |
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[331] | 184 | READ_IDLE, |
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| 185 | READ_DIR_REQ, |
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| 186 | READ_DIR_LOCK, |
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[477] | 187 | READ_IVT_LOCK, |
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| 188 | READ_WAIT, |
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[331] | 189 | READ_DIR_HIT, |
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| 190 | READ_HEAP_REQ, |
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| 191 | READ_HEAP_LOCK, |
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| 192 | READ_HEAP_WRITE, |
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| 193 | READ_HEAP_ERASE, |
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| 194 | READ_HEAP_LAST, |
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| 195 | READ_RSP, |
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| 196 | READ_TRT_LOCK, |
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| 197 | READ_TRT_SET, |
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| 198 | READ_TRT_REQ |
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| 199 | }; |
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| 200 | |
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| 201 | /* States of the WRITE fsm */ |
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[395] | 202 | enum write_fsm_state_e |
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| 203 | { |
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[331] | 204 | WRITE_IDLE, |
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| 205 | WRITE_NEXT, |
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| 206 | WRITE_DIR_REQ, |
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| 207 | WRITE_DIR_LOCK, |
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[477] | 208 | WRITE_IVT_LOCK_HIT_WB, |
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[331] | 209 | WRITE_DIR_HIT, |
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| 210 | WRITE_UPT_LOCK, |
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| 211 | WRITE_UPT_HEAP_LOCK, |
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| 212 | WRITE_UPT_REQ, |
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| 213 | WRITE_UPT_NEXT, |
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| 214 | WRITE_UPT_DEC, |
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| 215 | WRITE_RSP, |
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[477] | 216 | WRITE_MISS_IVT_LOCK, |
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[331] | 217 | WRITE_MISS_TRT_LOCK, |
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| 218 | WRITE_MISS_TRT_DATA, |
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| 219 | WRITE_MISS_TRT_SET, |
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| 220 | WRITE_MISS_XRAM_REQ, |
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[495] | 221 | WRITE_BC_DIR_READ, |
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[331] | 222 | WRITE_BC_TRT_LOCK, |
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[468] | 223 | WRITE_BC_IVT_LOCK, |
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[331] | 224 | WRITE_BC_DIR_INVAL, |
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| 225 | WRITE_BC_CC_SEND, |
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| 226 | WRITE_BC_XRAM_REQ, |
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| 227 | WRITE_WAIT |
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| 228 | }; |
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| 229 | |
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| 230 | /* States of the IXR_RSP fsm */ |
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[395] | 231 | enum ixr_rsp_fsm_state_e |
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| 232 | { |
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[331] | 233 | IXR_RSP_IDLE, |
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| 234 | IXR_RSP_ACK, |
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| 235 | IXR_RSP_TRT_ERASE, |
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| 236 | IXR_RSP_TRT_READ |
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| 237 | }; |
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| 238 | |
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| 239 | /* States of the XRAM_RSP fsm */ |
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[395] | 240 | enum xram_rsp_fsm_state_e |
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| 241 | { |
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[331] | 242 | XRAM_RSP_IDLE, |
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| 243 | XRAM_RSP_TRT_COPY, |
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| 244 | XRAM_RSP_TRT_DIRTY, |
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| 245 | XRAM_RSP_DIR_LOCK, |
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| 246 | XRAM_RSP_DIR_UPDT, |
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| 247 | XRAM_RSP_DIR_RSP, |
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[495] | 248 | XRAM_RSP_IVT_LOCK, |
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[331] | 249 | XRAM_RSP_INVAL_WAIT, |
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| 250 | XRAM_RSP_INVAL, |
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| 251 | XRAM_RSP_WRITE_DIRTY, |
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| 252 | XRAM_RSP_HEAP_REQ, |
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| 253 | XRAM_RSP_HEAP_ERASE, |
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| 254 | XRAM_RSP_HEAP_LAST, |
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| 255 | XRAM_RSP_ERROR_ERASE, |
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| 256 | XRAM_RSP_ERROR_RSP |
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| 257 | }; |
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| 258 | |
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| 259 | /* States of the IXR_CMD fsm */ |
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[395] | 260 | enum ixr_cmd_fsm_state_e |
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| 261 | { |
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[331] | 262 | IXR_CMD_READ_IDLE, |
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| 263 | IXR_CMD_WRITE_IDLE, |
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| 264 | IXR_CMD_CAS_IDLE, |
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| 265 | IXR_CMD_XRAM_IDLE, |
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[477] | 266 | IXR_CMD_CLEANUP_IDLE, |
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[495] | 267 | IXR_CMD_CONFIG_IDLE, |
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| 268 | IXR_CMD_READ_TRT, |
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| 269 | IXR_CMD_WRITE_TRT, |
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| 270 | IXR_CMD_CAS_TRT, |
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| 271 | IXR_CMD_XRAM_TRT, |
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| 272 | IXR_CMD_CLEANUP_TRT, |
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| 273 | IXR_CMD_CONFIG_TRT, |
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| 274 | IXR_CMD_READ_SEND, |
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| 275 | IXR_CMD_WRITE_SEND, |
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| 276 | IXR_CMD_CAS_SEND, |
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| 277 | IXR_CMD_XRAM_SEND, |
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| 278 | IXR_CMD_CLEANUP_DATA_SEND, |
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| 279 | IXR_CMD_CONFIG_SEND |
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[331] | 280 | }; |
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| 281 | |
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| 282 | /* States of the CAS fsm */ |
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[395] | 283 | enum cas_fsm_state_e |
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| 284 | { |
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[331] | 285 | CAS_IDLE, |
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| 286 | CAS_DIR_REQ, |
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| 287 | CAS_DIR_LOCK, |
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| 288 | CAS_DIR_HIT_READ, |
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| 289 | CAS_DIR_HIT_COMPARE, |
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| 290 | CAS_DIR_HIT_WRITE, |
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| 291 | CAS_UPT_LOCK, |
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| 292 | CAS_UPT_HEAP_LOCK, |
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| 293 | CAS_UPT_REQ, |
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| 294 | CAS_UPT_NEXT, |
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| 295 | CAS_BC_TRT_LOCK, |
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[468] | 296 | CAS_BC_IVT_LOCK, |
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[331] | 297 | CAS_BC_DIR_INVAL, |
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| 298 | CAS_BC_CC_SEND, |
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| 299 | CAS_BC_XRAM_REQ, |
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| 300 | CAS_RSP_FAIL, |
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| 301 | CAS_RSP_SUCCESS, |
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| 302 | CAS_MISS_TRT_LOCK, |
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| 303 | CAS_MISS_TRT_SET, |
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| 304 | CAS_MISS_XRAM_REQ, |
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| 305 | CAS_WAIT |
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| 306 | }; |
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| 307 | |
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| 308 | /* States of the CLEANUP fsm */ |
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[395] | 309 | enum cleanup_fsm_state_e |
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| 310 | { |
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[331] | 311 | CLEANUP_IDLE, |
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| 312 | CLEANUP_GET_NLINE, |
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[477] | 313 | CLEANUP_GET_DATA, |
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[331] | 314 | CLEANUP_DIR_REQ, |
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| 315 | CLEANUP_DIR_LOCK, |
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| 316 | CLEANUP_DIR_WRITE, |
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[477] | 317 | CLEANUP_IVT_LOCK_DATA, |
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| 318 | CLEANUP_IVT_CLEAR_DATA, |
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| 319 | CLEANUP_READ_RSP, |
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[331] | 320 | CLEANUP_HEAP_REQ, |
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| 321 | CLEANUP_HEAP_LOCK, |
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| 322 | CLEANUP_HEAP_SEARCH, |
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| 323 | CLEANUP_HEAP_CLEAN, |
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| 324 | CLEANUP_HEAP_FREE, |
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[468] | 325 | CLEANUP_IVT_LOCK, |
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| 326 | CLEANUP_IVT_DECREMENT, |
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| 327 | CLEANUP_IVT_CLEAR, |
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[331] | 328 | CLEANUP_WRITE_RSP, |
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[477] | 329 | CLEANUP_IXR_REQ, |
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| 330 | CLEANUP_WAIT, |
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[434] | 331 | CLEANUP_SEND_CLACK |
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[331] | 332 | }; |
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| 333 | |
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| 334 | /* States of the ALLOC_DIR fsm */ |
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[395] | 335 | enum alloc_dir_fsm_state_e |
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| 336 | { |
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[331] | 337 | ALLOC_DIR_RESET, |
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| 338 | ALLOC_DIR_READ, |
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| 339 | ALLOC_DIR_WRITE, |
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| 340 | ALLOC_DIR_CAS, |
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| 341 | ALLOC_DIR_CLEANUP, |
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[545] | 342 | ALLOC_DIR_XRAM_RSP, |
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| 343 | ALLOC_DIR_CONFIG |
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[331] | 344 | }; |
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| 345 | |
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| 346 | /* States of the ALLOC_TRT fsm */ |
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[395] | 347 | enum alloc_trt_fsm_state_e |
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| 348 | { |
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[331] | 349 | ALLOC_TRT_READ, |
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| 350 | ALLOC_TRT_WRITE, |
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| 351 | ALLOC_TRT_CAS, |
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| 352 | ALLOC_TRT_XRAM_RSP, |
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[477] | 353 | ALLOC_TRT_IXR_RSP, |
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[495] | 354 | ALLOC_TRT_CLEANUP, |
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| 355 | ALLOC_TRT_IXR_CMD, |
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| 356 | ALLOC_TRT_CONFIG |
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[331] | 357 | }; |
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| 358 | |
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| 359 | /* States of the ALLOC_UPT fsm */ |
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[395] | 360 | enum alloc_upt_fsm_state_e |
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| 361 | { |
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[331] | 362 | ALLOC_UPT_WRITE, |
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[468] | 363 | ALLOC_UPT_CAS, |
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| 364 | ALLOC_UPT_MULTI_ACK |
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[331] | 365 | }; |
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| 366 | |
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[468] | 367 | /* States of the ALLOC_IVT fsm */ |
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| 368 | enum alloc_ivt_fsm_state_e |
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| 369 | { |
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| 370 | ALLOC_IVT_WRITE, |
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[477] | 371 | ALLOC_IVT_READ, |
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[468] | 372 | ALLOC_IVT_XRAM_RSP, |
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| 373 | ALLOC_IVT_CLEANUP, |
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| 374 | ALLOC_IVT_CAS, |
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| 375 | ALLOC_IVT_CONFIG |
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| 376 | }; |
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| 377 | |
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[331] | 378 | /* States of the ALLOC_HEAP fsm */ |
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[395] | 379 | enum alloc_heap_fsm_state_e |
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| 380 | { |
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[331] | 381 | ALLOC_HEAP_RESET, |
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| 382 | ALLOC_HEAP_READ, |
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| 383 | ALLOC_HEAP_WRITE, |
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| 384 | ALLOC_HEAP_CAS, |
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| 385 | ALLOC_HEAP_CLEANUP, |
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[439] | 386 | ALLOC_HEAP_XRAM_RSP, |
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| 387 | ALLOC_HEAP_CONFIG |
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[331] | 388 | }; |
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| 389 | |
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| 390 | /* transaction type, pktid field */ |
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| 391 | enum transaction_type_e |
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| 392 | { |
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| 393 | // b3 unused |
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| 394 | // b2 READ / NOT READ |
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| 395 | // Si READ |
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| 396 | // b1 DATA / INS |
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| 397 | // b0 UNC / MISS |
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| 398 | // Si NOT READ |
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| 399 | // b1 accÚs table llsc type SW / other |
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| 400 | // b2 WRITE/CAS/LL/SC |
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[783] | 401 | TYPE_READ_DATA_UNC = 0x0, |
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| 402 | TYPE_READ_DATA_MISS = 0x1, |
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| 403 | TYPE_READ_INS_UNC = 0x2, |
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| 404 | TYPE_READ_INS_MISS = 0x3, |
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| 405 | TYPE_WRITE = 0x4, |
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| 406 | TYPE_CAS = 0x5, |
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| 407 | TYPE_LL = 0x6, |
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| 408 | TYPE_SC = 0x7 |
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[331] | 409 | }; |
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| 410 | |
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| 411 | /* SC return values */ |
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| 412 | enum sc_status_type_e |
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| 413 | { |
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[783] | 414 | SC_SUCCESS = 0x00000000, |
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| 415 | SC_FAIL = 0x00000001 |
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[331] | 416 | }; |
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| 417 | |
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[495] | 418 | // debug variables |
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[783] | 419 | bool m_debug; |
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| 420 | bool m_debug_previous_valid; |
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| 421 | size_t m_debug_previous_count; |
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| 422 | bool m_debug_previous_dirty; |
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| 423 | data_t * m_debug_previous_data; |
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| 424 | data_t * m_debug_data; |
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[331] | 425 | |
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| 426 | // instrumentation counters |
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[783] | 427 | uint32_t m_cpt_cycles; // Counter of cycles |
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[434] | 428 | |
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[783] | 429 | // Counters accessible in software (not yet but eventually) and tagged |
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| 430 | uint32_t m_cpt_reset_count; // Last cycle at which counters have been reset |
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| 431 | uint32_t m_cpt_read_local; // Number of local READ transactions |
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| 432 | uint32_t m_cpt_read_remote; // number of remote READ transactions |
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| 433 | uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs |
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[434] | 434 | |
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[783] | 435 | uint32_t m_cpt_write_local; // Number of local WRITE transactions |
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| 436 | uint32_t m_cpt_write_remote; // number of remote WRITE transactions |
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| 437 | uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs |
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| 438 | uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs |
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| 439 | uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs |
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| 440 | uint32_t m_cpt_write_ncc_miss; // Number of write on ncc line |
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[434] | 441 | |
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[783] | 442 | uint32_t m_cpt_ll_local; // Number of local LL transactions |
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| 443 | uint32_t m_cpt_ll_remote; // number of remote LL transactions |
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| 444 | uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs |
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[545] | 445 | |
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[783] | 446 | uint32_t m_cpt_sc_local; // Number of local SC transactions |
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| 447 | uint32_t m_cpt_sc_remote; // number of remote SC transactions |
---|
| 448 | uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs |
---|
[545] | 449 | |
---|
[783] | 450 | uint32_t m_cpt_cas_local; // Number of local SC transactions |
---|
| 451 | uint32_t m_cpt_cas_remote; // number of remote SC transactions |
---|
| 452 | uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs |
---|
[545] | 453 | |
---|
[783] | 454 | uint32_t m_cpt_update; // Number of requests causing an UPDATE |
---|
| 455 | uint32_t m_cpt_update_local; // Number of local UPDATE transactions |
---|
| 456 | uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions |
---|
| 457 | uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT |
---|
[545] | 458 | |
---|
[783] | 459 | uint32_t m_cpt_minval; // Number of requests causing M_INV |
---|
| 460 | uint32_t m_cpt_minval_local; // Number of local M_INV transactions |
---|
| 461 | uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions |
---|
| 462 | uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV |
---|
[545] | 463 | |
---|
[783] | 464 | uint32_t m_cpt_binval; // Number of BROADCAST INVAL |
---|
[545] | 465 | |
---|
[783] | 466 | uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions (all cleanup types) |
---|
| 467 | uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions (all cleanup types) |
---|
| 468 | uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs (all types) |
---|
[545] | 469 | |
---|
[783] | 470 | // Counters not accessible by software, but tagged |
---|
| 471 | uint32_t m_cpt_read_miss; // Number of MISS READ |
---|
| 472 | uint32_t m_cpt_write_miss; // Number of MISS WRITE |
---|
| 473 | uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions |
---|
| 474 | uint32_t m_cpt_write_broadcast; // Number of BROADCAST INVAL because write |
---|
[545] | 475 | |
---|
[783] | 476 | uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt |
---|
| 477 | uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt |
---|
| 478 | |
---|
| 479 | uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused |
---|
| 480 | uint32_t m_cpt_heap_slot_available; // NB HEAP slot available refresh at each cycles |
---|
| 481 | uint32_t m_cpt_heap_min_slot_available; // NB HEAP : Min of slot available |
---|
| 482 | |
---|
| 483 | uint32_t m_cpt_ncc_to_cc_read; // NB change from NCC to CC caused by a READ |
---|
| 484 | uint32_t m_cpt_ncc_to_cc_write; // NB change from NCC to CC caused by a WRITE |
---|
| 485 | |
---|
| 486 | uint32_t m_cpt_cleanup_data_local; // Number of local cleanups with data |
---|
| 487 | uint32_t m_cpt_cleanup_data_remote; // Number of remote cleanups with data |
---|
| 488 | uint32_t m_cpt_cleanup_data_cost; // Cost for cleanups with data |
---|
| 489 | |
---|
| 490 | uint32_t m_cpt_update_flits; // Number of flits for UPDATEs |
---|
| 491 | uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs |
---|
| 492 | |
---|
| 493 | uint32_t m_cpt_get; |
---|
| 494 | uint32_t m_cpt_put; |
---|
| 495 | |
---|
| 496 | // TODO: clean the following counters (not necessarily useful and well-implemented) |
---|
| 497 | uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK |
---|
| 498 | uint32_t m_cpt_read_fsm_n_dir_lock; // NB DIR LOCK |
---|
| 499 | uint32_t m_cpt_write_fsm_dir_lock; // wait DIR LOCK |
---|
| 500 | uint32_t m_cpt_write_fsm_n_dir_lock; // NB DIR LOCK |
---|
| 501 | uint32_t m_cpt_xram_rsp_fsm_dir_lock; // wait DIR LOCK |
---|
| 502 | uint32_t m_cpt_xram_rsp_fsm_n_dir_lock; // NB DIR LOCK |
---|
| 503 | uint32_t m_cpt_cas_fsm_dir_lock; // wait DIR LOCK |
---|
| 504 | uint32_t m_cpt_cas_fsm_n_dir_lock; // NB DIR LOCK |
---|
| 505 | uint32_t m_cpt_cleanup_fsm_dir_lock; // wait DIR LOCK |
---|
| 506 | uint32_t m_cpt_cleanup_fsm_n_dir_lock; // NB DIR LOCK |
---|
[477] | 507 | |
---|
[783] | 508 | uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused |
---|
| 509 | uint32_t m_cpt_read_fsm_dir_used; // NB cycles DIR LOCK used |
---|
| 510 | uint32_t m_cpt_write_fsm_dir_used; // NB cycles DIR LOCK used |
---|
| 511 | uint32_t m_cpt_cas_fsm_dir_used; // NB cycles DIR LOCK used |
---|
| 512 | uint32_t m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used |
---|
| 513 | uint32_t m_cpt_cleanup_fsm_dir_used; // NB cycles DIR LOCK used |
---|
[331] | 514 | |
---|
[783] | 515 | uint32_t m_cpt_read_fsm_trt_lock; // wait TRT LOCK |
---|
| 516 | uint32_t m_cpt_write_fsm_trt_lock; // wait TRT LOCK |
---|
| 517 | uint32_t m_cpt_cas_fsm_trt_lock; // wait TRT LOCK |
---|
| 518 | uint32_t m_cpt_xram_rsp_fsm_trt_lock; // wait TRT LOCK |
---|
| 519 | uint32_t m_cpt_ixr_fsm_trt_lock; // wait TRT LOCK |
---|
[477] | 520 | |
---|
[783] | 521 | uint32_t m_cpt_read_fsm_n_trt_lock; // NB TRT LOCK |
---|
| 522 | uint32_t m_cpt_write_fsm_n_trt_lock; // NB TRT LOCK |
---|
| 523 | uint32_t m_cpt_cas_fsm_n_trt_lock; // NB TRT LOCK |
---|
| 524 | uint32_t m_cpt_xram_rsp_fsm_n_trt_lock; // NB TRT LOCK |
---|
| 525 | uint32_t m_cpt_ixr_fsm_n_trt_lock; // NB TRT LOCK |
---|
[477] | 526 | |
---|
[783] | 527 | uint32_t m_cpt_read_fsm_trt_used; // NB cycles TRT LOCK used |
---|
| 528 | uint32_t m_cpt_write_fsm_trt_used; // NB cycles TRT LOCK used |
---|
| 529 | uint32_t m_cpt_cas_fsm_trt_used; // NB cycles TRT LOCK used |
---|
| 530 | uint32_t m_cpt_xram_rsp_fsm_trt_used; // NB cycles TRT LOCK used |
---|
| 531 | uint32_t m_cpt_ixr_fsm_trt_used; // NB cycles TRT LOCK used |
---|
[477] | 532 | |
---|
[783] | 533 | uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused |
---|
[477] | 534 | |
---|
[783] | 535 | uint32_t m_cpt_write_fsm_upt_lock; // wait UPT LOCK |
---|
| 536 | uint32_t m_cpt_xram_rsp_fsm_upt_lock; // wait UPT LOCK |
---|
| 537 | uint32_t m_cpt_multi_ack_fsm_upt_lock; // wait UPT LOCK |
---|
| 538 | uint32_t m_cpt_cleanup_fsm_ivt_lock; // wait UPT LOCK |
---|
| 539 | uint32_t m_cpt_cas_fsm_upt_lock; // wait UPT LOCK |
---|
[477] | 540 | |
---|
[783] | 541 | uint32_t m_cpt_write_fsm_n_upt_lock; // NB UPT LOCK |
---|
| 542 | uint32_t m_cpt_xram_rsp_fsm_n_upt_lock; // NB UPT LOCK |
---|
| 543 | uint32_t m_cpt_multi_ack_fsm_n_upt_lock; // NB UPT LOCK |
---|
| 544 | uint32_t m_cpt_cleanup_fsm_n_upt_lock; // NB UPT LOCK |
---|
| 545 | uint32_t m_cpt_cas_fsm_n_upt_lock; // NB UPT LOCK |
---|
[477] | 546 | |
---|
[783] | 547 | uint32_t m_cpt_write_fsm_upt_used; // NB cycles UPT LOCK used |
---|
| 548 | uint32_t m_cpt_xram_rsp_fsm_upt_used; // NB cycles UPT LOCK used |
---|
| 549 | uint32_t m_cpt_multi_ack_fsm_upt_used; // NB cycles UPT LOCK used |
---|
| 550 | uint32_t m_cpt_cleanup_fsm_ivt_used; // NB cycles UPT LOCK used |
---|
| 551 | uint32_t m_cpt_cas_fsm_upt_used; // NB cycles UPT LOCK used |
---|
[477] | 552 | |
---|
[783] | 553 | uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused |
---|
| 554 | uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused |
---|
[477] | 555 | |
---|
[783] | 556 | uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK |
---|
| 557 | uint32_t m_cpt_write_fsm_heap_lock; // wait HEAP LOCK |
---|
| 558 | uint32_t m_cpt_cas_fsm_heap_lock; // wait HEAP LOCK |
---|
| 559 | uint32_t m_cpt_cleanup_fsm_heap_lock; // wait HEAP LOCK |
---|
| 560 | uint32_t m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK |
---|
[477] | 561 | |
---|
[783] | 562 | uint32_t m_cpt_read_fsm_n_heap_lock; // NB HEAP LOCK |
---|
| 563 | uint32_t m_cpt_write_fsm_n_heap_lock; // NB HEAP LOCK |
---|
| 564 | uint32_t m_cpt_cas_fsm_n_heap_lock; // NB HEAP LOCK |
---|
| 565 | uint32_t m_cpt_cleanup_fsm_n_heap_lock; // NB HEAP LOCK |
---|
| 566 | uint32_t m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK |
---|
[477] | 567 | |
---|
[783] | 568 | uint32_t m_cpt_read_fsm_heap_used; // NB cycles HEAP LOCK used |
---|
| 569 | uint32_t m_cpt_write_fsm_heap_used; // NB cycles HEAP LOCK used |
---|
| 570 | uint32_t m_cpt_cas_fsm_heap_used; // NB cycles HEAP LOCK used |
---|
| 571 | uint32_t m_cpt_cleanup_fsm_heap_used; // NB cycles HEAP LOCK used |
---|
| 572 | uint32_t m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used |
---|
[477] | 573 | |
---|
[783] | 574 | uint32_t m_cpt_read_data_unc; |
---|
| 575 | uint32_t m_cpt_read_data_miss_CC; |
---|
| 576 | uint32_t m_cpt_read_ins_unc; |
---|
| 577 | uint32_t m_cpt_read_ins_miss; |
---|
| 578 | uint32_t m_cpt_read_ll_CC; |
---|
| 579 | uint32_t m_cpt_read_data_miss_NCC; |
---|
| 580 | uint32_t m_cpt_read_ll_NCC; |
---|
[477] | 581 | |
---|
[783] | 582 | size_t m_prev_count; |
---|
[477] | 583 | |
---|
[331] | 584 | protected: |
---|
| 585 | |
---|
| 586 | SC_HAS_PROCESS(VciMemCache); |
---|
| 587 | |
---|
| 588 | public: |
---|
[385] | 589 | sc_in<bool> p_clk; |
---|
| 590 | sc_in<bool> p_resetn; |
---|
[767] | 591 | sc_out<bool> p_irq; |
---|
[385] | 592 | soclib::caba::VciTarget<vci_param_int> p_vci_tgt; |
---|
| 593 | soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr; |
---|
[468] | 594 | soclib::caba::DspinInput<dspin_in_width> p_dspin_p2m; |
---|
| 595 | soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p; |
---|
| 596 | soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack; |
---|
[331] | 597 | |
---|
[545] | 598 | #if MONITOR_MEMCACHE_FSM == 1 |
---|
| 599 | sc_out<int> p_read_fsm; |
---|
| 600 | sc_out<int> p_write_fsm; |
---|
| 601 | sc_out<int> p_xram_rsp_fsm; |
---|
| 602 | sc_out<int> p_cas_fsm; |
---|
| 603 | sc_out<int> p_cleanup_fsm; |
---|
| 604 | sc_out<int> p_config_fsm; |
---|
| 605 | sc_out<int> p_alloc_heap_fsm; |
---|
| 606 | sc_out<int> p_alloc_dir_fsm; |
---|
| 607 | sc_out<int> p_alloc_trt_fsm; |
---|
| 608 | sc_out<int> p_alloc_upt_fsm; |
---|
| 609 | sc_out<int> p_alloc_ivt_fsm; |
---|
| 610 | sc_out<int> p_tgt_cmd_fsm; |
---|
| 611 | sc_out<int> p_tgt_rsp_fsm; |
---|
| 612 | sc_out<int> p_ixr_cmd_fsm; |
---|
| 613 | sc_out<int> p_ixr_rsp_fsm; |
---|
| 614 | sc_out<int> p_cc_send_fsm; |
---|
| 615 | sc_out<int> p_cc_receive_fsm; |
---|
| 616 | sc_out<int> p_multi_ack_fsm; |
---|
| 617 | #endif |
---|
| 618 | |
---|
[331] | 619 | VciMemCache( |
---|
| 620 | sc_module_name name, // Instance Name |
---|
[434] | 621 | const soclib::common::MappingTable &mtp, // Mapping table INT network |
---|
| 622 | const soclib::common::MappingTable &mtx, // Mapping table RAM network |
---|
| 623 | const soclib::common::IntTab &srcid_x, // global index RAM network |
---|
| 624 | const soclib::common::IntTab &tgtid_d, // global index INT network |
---|
[545] | 625 | const size_t x_width, // X width in platform |
---|
| 626 | const size_t y_width, // Y width in platform |
---|
[346] | 627 | const size_t nways, // Number of ways per set |
---|
| 628 | const size_t nsets, // Number of sets |
---|
| 629 | const size_t nwords, // Number of words per line |
---|
[434] | 630 | const size_t max_copies, // max number of copies |
---|
[395] | 631 | const size_t heap_size=HEAP_ENTRIES, |
---|
| 632 | const size_t trt_lines=TRT_ENTRIES, |
---|
| 633 | const size_t upt_lines=UPT_ENTRIES, |
---|
[468] | 634 | const size_t ivt_lines=IVT_ENTRIES, |
---|
[346] | 635 | const size_t debug_start_cycle=0, |
---|
| 636 | const bool debug_ok=false ); |
---|
[331] | 637 | |
---|
| 638 | ~VciMemCache(); |
---|
| 639 | |
---|
[644] | 640 | void reset_counters(); |
---|
[767] | 641 | void print_stats(bool activity_counters = true, bool stats = false); |
---|
[604] | 642 | void print_trace( size_t detailled = 0 ); |
---|
[449] | 643 | void cache_monitor(addr_t addr); |
---|
[385] | 644 | void start_monitor(addr_t addr, addr_t length); |
---|
[331] | 645 | void stop_monitor(); |
---|
| 646 | |
---|
| 647 | private: |
---|
| 648 | |
---|
| 649 | void transition(); |
---|
| 650 | void genMoore(); |
---|
[449] | 651 | void check_monitor(addr_t addr, data_t data, bool read); |
---|
[545] | 652 | uint32_t req_distance(uint32_t req_srcid); |
---|
[767] | 653 | uint32_t min_value(uint32_t old_value, uint32_t new_value); |
---|
[545] | 654 | bool is_local_req(uint32_t req_srcid); |
---|
[611] | 655 | int read_instrumentation(uint32_t regr, uint32_t & rdata); |
---|
[331] | 656 | |
---|
| 657 | // Component attributes |
---|
[434] | 658 | std::list<soclib::common::Segment> m_seglist; // segments allocated |
---|
[346] | 659 | size_t m_nseg; // number of segments |
---|
| 660 | soclib::common::Segment **m_seg; // array of segments pointers |
---|
[434] | 661 | size_t m_seg_config; // config segment index |
---|
| 662 | const size_t m_srcid_x; // global index on RAM network |
---|
[346] | 663 | const size_t m_initiators; // Number of initiators |
---|
| 664 | const size_t m_heap_size; // Size of the heap |
---|
| 665 | const size_t m_ways; // Number of ways in a set |
---|
| 666 | const size_t m_sets; // Number of cache sets |
---|
| 667 | const size_t m_words; // Number of words in a line |
---|
[767] | 668 | size_t m_x_self; // X self coordinate |
---|
| 669 | size_t m_y_self; // Y self coordinate |
---|
| 670 | const size_t m_x_width; // number of x bits in platform |
---|
| 671 | const size_t m_y_width; // number of y bits in platform |
---|
[346] | 672 | size_t m_debug_start_cycle; |
---|
| 673 | bool m_debug_ok; |
---|
| 674 | uint32_t m_trt_lines; |
---|
| 675 | TransactionTab m_trt; // xram transaction table |
---|
| 676 | uint32_t m_upt_lines; |
---|
[468] | 677 | UpdateTab m_upt; // pending update |
---|
| 678 | UpdateTab m_ivt; // pending invalidate |
---|
[346] | 679 | CacheDirectory m_cache_directory; // data cache directory |
---|
| 680 | CacheData m_cache_data; // data array[set][way][word] |
---|
| 681 | HeapDirectory m_heap; // heap for copies |
---|
| 682 | size_t m_max_copies; // max number of copies in heap |
---|
[331] | 683 | GenericLLSCGlobalTable |
---|
[434] | 684 | < 32 , // number of slots |
---|
| 685 | 4096, // number of processors in the system |
---|
| 686 | 8000, // registration life (# of LL operations) |
---|
| 687 | addr_t > m_llsc_table; // ll/sc registration table |
---|
[331] | 688 | |
---|
| 689 | // adress masks |
---|
[385] | 690 | const soclib::common::AddressMaskingTable<addr_t> m_x; |
---|
| 691 | const soclib::common::AddressMaskingTable<addr_t> m_y; |
---|
| 692 | const soclib::common::AddressMaskingTable<addr_t> m_z; |
---|
| 693 | const soclib::common::AddressMaskingTable<addr_t> m_nline; |
---|
[331] | 694 | |
---|
| 695 | // broadcast address |
---|
[395] | 696 | uint32_t m_broadcast_boundaries; |
---|
[331] | 697 | |
---|
[611] | 698 | // configuration interface constants |
---|
| 699 | const uint32_t m_config_addr_mask; |
---|
| 700 | const uint32_t m_config_regr_width; |
---|
| 701 | const uint32_t m_config_func_width; |
---|
| 702 | const uint32_t m_config_regr_idx_mask; |
---|
| 703 | const uint32_t m_config_func_idx_mask; |
---|
| 704 | |
---|
[331] | 705 | // Fifo between TGT_CMD fsm and READ fsm |
---|
[385] | 706 | GenericFifo<addr_t> m_cmd_read_addr_fifo; |
---|
[331] | 707 | GenericFifo<size_t> m_cmd_read_length_fifo; |
---|
| 708 | GenericFifo<size_t> m_cmd_read_srcid_fifo; |
---|
| 709 | GenericFifo<size_t> m_cmd_read_trdid_fifo; |
---|
| 710 | GenericFifo<size_t> m_cmd_read_pktid_fifo; |
---|
| 711 | |
---|
| 712 | // Fifo between TGT_CMD fsm and WRITE fsm |
---|
[385] | 713 | GenericFifo<addr_t> m_cmd_write_addr_fifo; |
---|
[331] | 714 | GenericFifo<bool> m_cmd_write_eop_fifo; |
---|
| 715 | GenericFifo<size_t> m_cmd_write_srcid_fifo; |
---|
| 716 | GenericFifo<size_t> m_cmd_write_trdid_fifo; |
---|
| 717 | GenericFifo<size_t> m_cmd_write_pktid_fifo; |
---|
| 718 | GenericFifo<data_t> m_cmd_write_data_fifo; |
---|
| 719 | GenericFifo<be_t> m_cmd_write_be_fifo; |
---|
| 720 | |
---|
| 721 | // Fifo between TGT_CMD fsm and CAS fsm |
---|
[385] | 722 | GenericFifo<addr_t> m_cmd_cas_addr_fifo; |
---|
[331] | 723 | GenericFifo<bool> m_cmd_cas_eop_fifo; |
---|
| 724 | GenericFifo<size_t> m_cmd_cas_srcid_fifo; |
---|
| 725 | GenericFifo<size_t> m_cmd_cas_trdid_fifo; |
---|
| 726 | GenericFifo<size_t> m_cmd_cas_pktid_fifo; |
---|
| 727 | GenericFifo<data_t> m_cmd_cas_wdata_fifo; |
---|
| 728 | |
---|
[403] | 729 | // Fifo between CC_RECEIVE fsm and CLEANUP fsm |
---|
[331] | 730 | GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo; |
---|
| 731 | |
---|
[403] | 732 | // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm |
---|
[331] | 733 | GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo; |
---|
| 734 | |
---|
[430] | 735 | // Buffer between TGT_CMD fsm and TGT_RSP fsm |
---|
| 736 | // (segmentation violation response request) |
---|
| 737 | sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req; |
---|
[434] | 738 | |
---|
| 739 | sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata; |
---|
| 740 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error; |
---|
[430] | 741 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid; |
---|
| 742 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid; |
---|
| 743 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid; |
---|
[331] | 744 | |
---|
[434] | 745 | sc_signal<addr_t> r_tgt_cmd_config_addr; |
---|
| 746 | sc_signal<size_t> r_tgt_cmd_config_cmd; |
---|
| 747 | |
---|
[495] | 748 | ////////////////////////////////////////////////// |
---|
| 749 | // Registers controlled by the TGT_CMD fsm |
---|
| 750 | ////////////////////////////////////////////////// |
---|
| 751 | |
---|
| 752 | sc_signal<int> r_tgt_cmd_fsm; |
---|
| 753 | |
---|
[331] | 754 | /////////////////////////////////////////////////////// |
---|
[434] | 755 | // Registers controlled by the CONFIG fsm |
---|
| 756 | /////////////////////////////////////////////////////// |
---|
| 757 | |
---|
[495] | 758 | sc_signal<int> r_config_fsm; // FSM state |
---|
| 759 | sc_signal<bool> r_config_lock; // lock protecting exclusive access |
---|
| 760 | sc_signal<int> r_config_cmd; // config request type |
---|
| 761 | sc_signal<addr_t> r_config_address; // target buffer physical address |
---|
| 762 | sc_signal<size_t> r_config_srcid; // config request srcid |
---|
| 763 | sc_signal<size_t> r_config_trdid; // config request trdid |
---|
| 764 | sc_signal<size_t> r_config_pktid; // config request pktid |
---|
| 765 | sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled |
---|
| 766 | sc_signal<size_t> r_config_rsp_lines; // number of lines not completed |
---|
| 767 | sc_signal<size_t> r_config_dir_way; // DIR: selected way |
---|
| 768 | sc_signal<bool> r_config_dir_lock; // DIR: locked entry |
---|
| 769 | sc_signal<size_t> r_config_dir_count; // DIR: number of copies |
---|
| 770 | sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast) |
---|
| 771 | sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID |
---|
| 772 | sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type |
---|
| 773 | sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP |
---|
| 774 | sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP |
---|
| 775 | sc_signal<size_t> r_config_trt_index; // selected entry in TRT |
---|
| 776 | sc_signal<size_t> r_config_ivt_index; // selected entry in IVT |
---|
[439] | 777 | |
---|
[495] | 778 | // Buffer between CONFIG fsm and IXR_CMD fsm |
---|
| 779 | sc_signal<bool> r_config_to_ixr_cmd_req; // valid request |
---|
| 780 | sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index |
---|
[434] | 781 | |
---|
| 782 | // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) |
---|
| 783 | sc_signal<bool> r_config_to_tgt_rsp_req; // valid request |
---|
| 784 | sc_signal<bool> r_config_to_tgt_rsp_error; // error response |
---|
| 785 | sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 786 | sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 787 | sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 788 | |
---|
| 789 | // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval) |
---|
| 790 | sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request |
---|
| 791 | sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request |
---|
[439] | 792 | sc_signal<addr_t> r_config_to_cc_send_nline; // line index |
---|
[434] | 793 | sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index |
---|
[439] | 794 | GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 795 | GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid |
---|
[434] | 796 | |
---|
| 797 | /////////////////////////////////////////////////////// |
---|
[331] | 798 | // Registers controlled by the READ fsm |
---|
| 799 | /////////////////////////////////////////////////////// |
---|
| 800 | |
---|
[495] | 801 | sc_signal<int> r_read_fsm; // FSM state |
---|
| 802 | sc_signal<size_t> r_read_copy; // Srcid of the first copy |
---|
| 803 | sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy |
---|
| 804 | sc_signal<bool> r_read_copy_inst; // Type of the first copy |
---|
| 805 | sc_signal<tag_t> r_read_tag; // cache line tag (in directory) |
---|
| 806 | sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) |
---|
| 807 | sc_signal<bool> r_read_lock; // lock bit (in directory) |
---|
| 808 | sc_signal<bool> r_read_dirty; // dirty bit (in directory) |
---|
| 809 | sc_signal<size_t> r_read_count; // number of copies |
---|
| 810 | sc_signal<size_t> r_read_ptr; // pointer to the heap |
---|
| 811 | sc_signal<data_t> * r_read_data; // data (one cache line) |
---|
| 812 | sc_signal<size_t> r_read_way; // associative way (in cache) |
---|
| 813 | sc_signal<size_t> r_read_trt_index; // Transaction Table index |
---|
| 814 | sc_signal<size_t> r_read_next_ptr; // Next entry to point to |
---|
| 815 | sc_signal<bool> r_read_last_free; // Last free entry |
---|
| 816 | sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table |
---|
[331] | 817 | |
---|
[495] | 818 | // Buffer between READ fsm and IXR_CMD fsm |
---|
| 819 | sc_signal<bool> r_read_to_ixr_cmd_req; // valid request |
---|
| 820 | sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index |
---|
[331] | 821 | |
---|
| 822 | // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) |
---|
[495] | 823 | sc_signal<bool> r_read_to_tgt_rsp_req; // valid request |
---|
| 824 | sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 825 | sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 826 | sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 827 | sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) |
---|
| 828 | sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response |
---|
| 829 | sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response |
---|
| 830 | sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table |
---|
[331] | 831 | |
---|
[477] | 832 | //RWT: Buffer between READ fsm and CC_SEND fsm (send inval) |
---|
| 833 | sc_signal<bool> r_read_to_cc_send_req; |
---|
| 834 | sc_signal<size_t> r_read_to_cc_send_dest; |
---|
| 835 | sc_signal<addr_t> r_read_to_cc_send_nline; |
---|
| 836 | sc_signal<bool> r_read_to_cc_send_inst; |
---|
| 837 | |
---|
| 838 | //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache) |
---|
| 839 | sc_signal<bool> r_read_to_cleanup_req; // valid request |
---|
| 840 | sc_signal<addr_t> r_read_to_cleanup_nline; // cache line index |
---|
| 841 | sc_signal<size_t> r_read_to_cleanup_srcid; |
---|
[767] | 842 | sc_signal<size_t> r_read_to_cleanup_inst; |
---|
[477] | 843 | sc_signal<size_t> r_read_to_cleanup_length; |
---|
| 844 | sc_signal<size_t> r_read_to_cleanup_first_word; |
---|
| 845 | sc_signal<bool> r_read_to_cleanup_cached_read; |
---|
| 846 | sc_signal<bool> r_read_to_cleanup_is_ll; |
---|
| 847 | sc_signal<addr_t> r_read_to_cleanup_addr; |
---|
| 848 | sc_signal<addr_t> r_read_to_cleanup_ll_key; |
---|
| 849 | |
---|
| 850 | //RWT: |
---|
| 851 | sc_signal<bool> r_read_coherent; // State of the cache slot after transaction |
---|
| 852 | sc_signal<bool> r_read_ll_done; |
---|
| 853 | |
---|
[331] | 854 | /////////////////////////////////////////////////////////////// |
---|
| 855 | // Registers controlled by the WRITE fsm |
---|
| 856 | /////////////////////////////////////////////////////////////// |
---|
| 857 | |
---|
[495] | 858 | sc_signal<int> r_write_fsm; // FSM state |
---|
| 859 | sc_signal<addr_t> r_write_address; // first word address |
---|
| 860 | sc_signal<size_t> r_write_word_index; // first word index in line |
---|
| 861 | sc_signal<size_t> r_write_word_count; // number of words in line |
---|
| 862 | sc_signal<size_t> r_write_srcid; // transaction srcid |
---|
| 863 | sc_signal<size_t> r_write_trdid; // transaction trdid |
---|
| 864 | sc_signal<size_t> r_write_pktid; // transaction pktid |
---|
| 865 | sc_signal<data_t> * r_write_data; // data (one cache line) |
---|
| 866 | sc_signal<be_t> * r_write_be; // one byte enable per word |
---|
| 867 | sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF) |
---|
| 868 | sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) |
---|
| 869 | sc_signal<bool> r_write_lock; // lock bit (in directory) |
---|
| 870 | sc_signal<tag_t> r_write_tag; // cache line tag (in directory) |
---|
| 871 | sc_signal<size_t> r_write_copy; // first owner of the line |
---|
| 872 | sc_signal<size_t> r_write_copy_cache; // first owner of the line |
---|
| 873 | sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? |
---|
| 874 | sc_signal<size_t> r_write_count; // number of copies |
---|
| 875 | sc_signal<size_t> r_write_ptr; // pointer to the heap |
---|
| 876 | sc_signal<size_t> r_write_next_ptr; // next pointer to the heap |
---|
| 877 | sc_signal<bool> r_write_to_dec; // need to decrement update counter |
---|
| 878 | sc_signal<size_t> r_write_way; // way of the line |
---|
| 879 | sc_signal<size_t> r_write_trt_index; // index in Transaction Table |
---|
| 880 | sc_signal<size_t> r_write_upt_index; // index in Update Table |
---|
| 881 | sc_signal<bool> r_write_sc_fail; // sc command failed |
---|
[545] | 882 | sc_signal<data_t> r_write_sc_key; // sc command key |
---|
| 883 | sc_signal<bool> r_write_bc_data_we; // Write enable for data buffer |
---|
[542] | 884 | |
---|
[331] | 885 | // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
| 886 | sc_signal<bool> r_write_to_tgt_rsp_req; // valid request |
---|
| 887 | sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid |
---|
| 888 | sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid |
---|
| 889 | sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid |
---|
| 890 | sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed |
---|
| 891 | |
---|
[495] | 892 | // Buffer between WRITE fsm and IXR_CMD fsm |
---|
| 893 | sc_signal<bool> r_write_to_ixr_cmd_req; // valid request |
---|
| 894 | sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index |
---|
[331] | 895 | |
---|
| 896 | // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) |
---|
| 897 | sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request |
---|
| 898 | sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request |
---|
| 899 | sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index |
---|
| 900 | sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table |
---|
| 901 | sc_signal<data_t> * r_write_to_cc_send_data; // data (one cache line) |
---|
| 902 | sc_signal<be_t> * r_write_to_cc_send_be; // word enable |
---|
| 903 | sc_signal<size_t> r_write_to_cc_send_count; // number of words in line |
---|
| 904 | sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line |
---|
| 905 | GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 906 | GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids |
---|
[385] | 907 | |
---|
[331] | 908 | // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) |
---|
| 909 | sc_signal<bool> r_write_to_multi_ack_req; // valid request |
---|
| 910 | sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table |
---|
| 911 | |
---|
[477] | 912 | // RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state) |
---|
| 913 | sc_signal<bool> r_write_to_cleanup_req; // valid request |
---|
| 914 | sc_signal<addr_t> r_write_to_cleanup_nline; // cache line index |
---|
| 915 | |
---|
| 916 | // RWT |
---|
| 917 | sc_signal<bool> r_write_coherent; // cache slot state after transaction |
---|
| 918 | |
---|
| 919 | //Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT) |
---|
| 920 | sc_signal<bool> r_write_to_cc_send_req; |
---|
| 921 | sc_signal<size_t> r_write_to_cc_send_dest; |
---|
| 922 | |
---|
| 923 | |
---|
[331] | 924 | ///////////////////////////////////////////////////////// |
---|
| 925 | // Registers controlled by MULTI_ACK fsm |
---|
| 926 | ////////////////////////////////////////////////////////// |
---|
| 927 | |
---|
| 928 | sc_signal<int> r_multi_ack_fsm; // FSM state |
---|
| 929 | sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table |
---|
| 930 | sc_signal<size_t> r_multi_ack_srcid; // pending write srcid |
---|
| 931 | sc_signal<size_t> r_multi_ack_trdid; // pending write trdid |
---|
| 932 | sc_signal<size_t> r_multi_ack_pktid; // pending write pktid |
---|
| 933 | sc_signal<addr_t> r_multi_ack_nline; // pending write nline |
---|
| 934 | |
---|
| 935 | // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) |
---|
| 936 | sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request |
---|
| 937 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 938 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 939 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 940 | |
---|
| 941 | /////////////////////////////////////////////////////// |
---|
| 942 | // Registers controlled by CLEANUP fsm |
---|
| 943 | /////////////////////////////////////////////////////// |
---|
| 944 | |
---|
| 945 | sc_signal<int> r_cleanup_fsm; // FSM state |
---|
| 946 | sc_signal<size_t> r_cleanup_srcid; // transaction srcid |
---|
| 947 | sc_signal<bool> r_cleanup_inst; // Instruction or Data ? |
---|
| 948 | sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index |
---|
| 949 | sc_signal<addr_t> r_cleanup_nline; // cache line index |
---|
| 950 | |
---|
| 951 | |
---|
| 952 | sc_signal<copy_t> r_cleanup_copy; // first copy |
---|
| 953 | sc_signal<copy_t> r_cleanup_copy_cache; // first copy |
---|
| 954 | sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy |
---|
| 955 | sc_signal<copy_t> r_cleanup_count; // number of copies |
---|
| 956 | sc_signal<size_t> r_cleanup_ptr; // pointer to the heap |
---|
| 957 | sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap |
---|
| 958 | sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry |
---|
| 959 | sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry |
---|
| 960 | sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry |
---|
| 961 | sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap |
---|
| 962 | sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory) |
---|
| 963 | sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory) |
---|
| 964 | sc_signal<bool> r_cleanup_lock; // lock bit (in directory) |
---|
| 965 | sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory) |
---|
| 966 | sc_signal<size_t> r_cleanup_way; // associative way (in cache) |
---|
| 967 | |
---|
[434] | 968 | sc_signal<size_t> r_cleanup_write_srcid; // srcid of write rsp |
---|
[331] | 969 | sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp |
---|
| 970 | sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp |
---|
| 971 | |
---|
[434] | 972 | sc_signal<bool> r_cleanup_need_rsp; // write response required |
---|
| 973 | sc_signal<bool> r_cleanup_need_ack; // config acknowledge required |
---|
| 974 | |
---|
[331] | 975 | sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) |
---|
| 976 | |
---|
| 977 | // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
| 978 | sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request |
---|
| 979 | sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid |
---|
| 980 | sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid |
---|
| 981 | sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid |
---|
[477] | 982 | sc_signal<addr_t> r_cleanup_to_tgt_rsp_ll_key; |
---|
[331] | 983 | |
---|
[477] | 984 | //RWT |
---|
| 985 | sc_signal<size_t> r_cleanup_read_srcid; |
---|
| 986 | sc_signal<size_t> r_cleanup_read_trdid; |
---|
| 987 | sc_signal<size_t> r_cleanup_read_pktid; |
---|
| 988 | sc_signal<bool> r_cleanup_read_need_rsp; |
---|
| 989 | sc_signal<bool> r_cleanup_to_tgt_rsp_type; |
---|
| 990 | sc_signal<data_t> * r_cleanup_to_tgt_rsp_data; |
---|
| 991 | sc_signal<size_t> r_cleanup_to_tgt_rsp_length; |
---|
| 992 | sc_signal<size_t> r_cleanup_to_tgt_rsp_first_word; |
---|
| 993 | |
---|
[331] | 994 | /////////////////////////////////////////////////////// |
---|
| 995 | // Registers controlled by CAS fsm |
---|
| 996 | /////////////////////////////////////////////////////// |
---|
| 997 | |
---|
[495] | 998 | sc_signal<int> r_cas_fsm; // FSM state |
---|
| 999 | sc_signal<data_t> r_cas_wdata; // write data word |
---|
| 1000 | sc_signal<data_t> * r_cas_rdata; // read data word |
---|
| 1001 | sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing |
---|
| 1002 | sc_signal<size_t> r_cas_cpt; // size of command |
---|
| 1003 | sc_signal<copy_t> r_cas_copy; // Srcid of the first copy |
---|
| 1004 | sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy |
---|
| 1005 | sc_signal<bool> r_cas_copy_inst; // Type of the first copy |
---|
| 1006 | sc_signal<size_t> r_cas_count; // number of copies |
---|
| 1007 | sc_signal<size_t> r_cas_ptr; // pointer to the heap |
---|
| 1008 | sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap |
---|
| 1009 | sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory) |
---|
| 1010 | sc_signal<bool> r_cas_dirty; // dirty bit (in directory) |
---|
| 1011 | sc_signal<size_t> r_cas_way; // way in directory |
---|
| 1012 | sc_signal<size_t> r_cas_set; // set in directory |
---|
| 1013 | sc_signal<data_t> r_cas_tag; // cache line tag (in directory) |
---|
| 1014 | sc_signal<size_t> r_cas_trt_index; // Transaction Table index |
---|
| 1015 | sc_signal<size_t> r_cas_upt_index; // Update Table index |
---|
| 1016 | sc_signal<data_t> * r_cas_data; // cache line data |
---|
[331] | 1017 | |
---|
[477] | 1018 | sc_signal<bool> r_cas_coherent; |
---|
| 1019 | |
---|
[331] | 1020 | // Buffer between CAS fsm and IXR_CMD fsm (XRAM write) |
---|
| 1021 | sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request |
---|
[495] | 1022 | sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index |
---|
[331] | 1023 | |
---|
| 1024 | // Buffer between CAS fsm and TGT_RSP fsm |
---|
| 1025 | sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request |
---|
| 1026 | sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word |
---|
| 1027 | sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 1028 | sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 1029 | sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 1030 | |
---|
| 1031 | // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches) |
---|
| 1032 | sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request |
---|
| 1033 | sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request |
---|
| 1034 | sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index |
---|
| 1035 | sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table |
---|
| 1036 | sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word) |
---|
| 1037 | sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS |
---|
| 1038 | sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word) |
---|
| 1039 | sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line |
---|
| 1040 | GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 1041 | GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids |
---|
[385] | 1042 | |
---|
[331] | 1043 | //////////////////////////////////////////////////// |
---|
| 1044 | // Registers controlled by the IXR_RSP fsm |
---|
| 1045 | //////////////////////////////////////////////////// |
---|
| 1046 | |
---|
[495] | 1047 | sc_signal<int> r_ixr_rsp_fsm; // FSM state |
---|
| 1048 | sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index |
---|
| 1049 | sc_signal<size_t> r_ixr_rsp_cpt; // word counter |
---|
[331] | 1050 | |
---|
[495] | 1051 | // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) |
---|
| 1052 | sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit |
---|
| 1053 | |
---|
[331] | 1054 | // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) |
---|
[495] | 1055 | sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry |
---|
[331] | 1056 | |
---|
| 1057 | //////////////////////////////////////////////////// |
---|
| 1058 | // Registers controlled by the XRAM_RSP fsm |
---|
| 1059 | //////////////////////////////////////////////////// |
---|
| 1060 | |
---|
| 1061 | sc_signal<int> r_xram_rsp_fsm; // FSM state |
---|
| 1062 | sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index |
---|
| 1063 | TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer |
---|
| 1064 | sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate |
---|
| 1065 | sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit |
---|
| 1066 | sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit |
---|
| 1067 | sc_signal<size_t> r_xram_rsp_victim_way; // victim line way |
---|
| 1068 | sc_signal<size_t> r_xram_rsp_victim_set; // victim line set |
---|
| 1069 | sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index |
---|
| 1070 | sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy |
---|
| 1071 | sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy |
---|
| 1072 | sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy |
---|
| 1073 | sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies |
---|
| 1074 | sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap |
---|
| 1075 | sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data |
---|
[468] | 1076 | sc_signal<size_t> r_xram_rsp_ivt_index; // IVT entry index |
---|
[331] | 1077 | sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap |
---|
[767] | 1078 | sc_signal<bool> r_xram_rsp_rerror_irq; // WRITE MISS rerror irq |
---|
| 1079 | sc_signal<bool> r_xram_rsp_rerror_irq_enable; // WRITE MISS rerror irq enable |
---|
| 1080 | sc_signal<addr_t> r_xram_rsp_rerror_address; // WRITE MISS rerror address |
---|
| 1081 | sc_signal<size_t> r_xram_rsp_rerror_rsrcid; // WRITE MISS rerror srcid |
---|
[331] | 1082 | |
---|
| 1083 | // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) |
---|
| 1084 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request |
---|
| 1085 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 1086 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 1087 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 1088 | sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line) |
---|
| 1089 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index |
---|
| 1090 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response |
---|
| 1091 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester |
---|
[385] | 1092 | sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table |
---|
[331] | 1093 | |
---|
| 1094 | // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches) |
---|
| 1095 | sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request |
---|
| 1096 | sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request |
---|
| 1097 | sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index; |
---|
| 1098 | sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry |
---|
| 1099 | GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 1100 | GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids |
---|
[385] | 1101 | |
---|
[495] | 1102 | // Buffer between XRAM_RSP fsm and IXR_CMD fsm |
---|
[331] | 1103 | sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request |
---|
[495] | 1104 | sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index |
---|
[331] | 1105 | |
---|
[477] | 1106 | //RWT |
---|
| 1107 | sc_signal<bool> r_xram_rsp_victim_coherent; // victim's cache slot state |
---|
| 1108 | sc_signal<bool> r_xram_rsp_coherent; // coherence of the read |
---|
[331] | 1109 | //////////////////////////////////////////////////// |
---|
| 1110 | // Registers controlled by the IXR_CMD fsm |
---|
| 1111 | //////////////////////////////////////////////////// |
---|
| 1112 | |
---|
| 1113 | sc_signal<int> r_ixr_cmd_fsm; |
---|
[495] | 1114 | sc_signal<size_t> r_ixr_cmd_word; // word index for a put |
---|
| 1115 | sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value |
---|
| 1116 | sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM |
---|
| 1117 | sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer |
---|
| 1118 | sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET) |
---|
[331] | 1119 | |
---|
| 1120 | //////////////////////////////////////////////////// |
---|
| 1121 | // Registers controlled by TGT_RSP fsm |
---|
| 1122 | //////////////////////////////////////////////////// |
---|
| 1123 | |
---|
| 1124 | sc_signal<int> r_tgt_rsp_fsm; |
---|
| 1125 | sc_signal<size_t> r_tgt_rsp_cpt; |
---|
[362] | 1126 | sc_signal<bool> r_tgt_rsp_key_sent; |
---|
[331] | 1127 | |
---|
| 1128 | //////////////////////////////////////////////////// |
---|
| 1129 | // Registers controlled by CC_SEND fsm |
---|
| 1130 | //////////////////////////////////////////////////// |
---|
| 1131 | |
---|
| 1132 | sc_signal<int> r_cc_send_fsm; |
---|
| 1133 | sc_signal<size_t> r_cc_send_cpt; |
---|
| 1134 | sc_signal<bool> r_cc_send_inst; |
---|
| 1135 | |
---|
| 1136 | //////////////////////////////////////////////////// |
---|
| 1137 | // Registers controlled by CC_RECEIVE fsm |
---|
| 1138 | //////////////////////////////////////////////////// |
---|
| 1139 | |
---|
| 1140 | sc_signal<int> r_cc_receive_fsm; |
---|
| 1141 | |
---|
| 1142 | //////////////////////////////////////////////////// |
---|
| 1143 | // Registers controlled by ALLOC_DIR fsm |
---|
| 1144 | //////////////////////////////////////////////////// |
---|
| 1145 | |
---|
| 1146 | sc_signal<int> r_alloc_dir_fsm; |
---|
| 1147 | sc_signal<unsigned> r_alloc_dir_reset_cpt; |
---|
| 1148 | |
---|
| 1149 | //////////////////////////////////////////////////// |
---|
| 1150 | // Registers controlled by ALLOC_TRT fsm |
---|
| 1151 | //////////////////////////////////////////////////// |
---|
| 1152 | |
---|
| 1153 | sc_signal<int> r_alloc_trt_fsm; |
---|
| 1154 | |
---|
| 1155 | //////////////////////////////////////////////////// |
---|
| 1156 | // Registers controlled by ALLOC_UPT fsm |
---|
| 1157 | //////////////////////////////////////////////////// |
---|
| 1158 | |
---|
| 1159 | sc_signal<int> r_alloc_upt_fsm; |
---|
| 1160 | |
---|
| 1161 | //////////////////////////////////////////////////// |
---|
[468] | 1162 | // Registers controlled by ALLOC_IVT fsm |
---|
| 1163 | //////////////////////////////////////////////////// |
---|
| 1164 | |
---|
| 1165 | sc_signal<int> r_alloc_ivt_fsm; |
---|
| 1166 | |
---|
| 1167 | //////////////////////////////////////////////////// |
---|
[331] | 1168 | // Registers controlled by ALLOC_HEAP fsm |
---|
| 1169 | //////////////////////////////////////////////////// |
---|
| 1170 | |
---|
| 1171 | sc_signal<int> r_alloc_heap_fsm; |
---|
| 1172 | sc_signal<unsigned> r_alloc_heap_reset_cpt; |
---|
[477] | 1173 | |
---|
| 1174 | |
---|
| 1175 | //////////////////////////////////////////////////// |
---|
| 1176 | // REGISTERS FOR ODCCP |
---|
| 1177 | //////////////////////////////////////////////////// |
---|
| 1178 | |
---|
| 1179 | sc_signal<uint32_t> r_cleanup_data_index; |
---|
| 1180 | sc_signal<uint32_t> r_cleanup_trdid; |
---|
| 1181 | sc_signal<uint32_t> r_cleanup_pktid; |
---|
| 1182 | sc_signal<bool> r_cleanup_coherent; |
---|
| 1183 | sc_signal<data_t> *r_cleanup_data; |
---|
| 1184 | sc_signal<data_t> *r_cleanup_old_data; |
---|
| 1185 | sc_signal<bool> r_cleanup_contains_data; |
---|
| 1186 | |
---|
| 1187 | sc_signal<bool> r_cleanup_ncc; |
---|
| 1188 | sc_signal<bool> r_cleanup_to_ixr_cmd_ncc_l1_dirty; |
---|
| 1189 | sc_signal<bool> r_xram_rsp_to_ixr_cmd_inval_ncc_pending; |
---|
| 1190 | |
---|
| 1191 | sc_signal<bool> r_cleanup_to_ixr_cmd_req; |
---|
| 1192 | sc_signal<data_t> *r_cleanup_to_ixr_cmd_data; |
---|
| 1193 | sc_signal<uint32_t> r_cleanup_to_ixr_cmd_srcid; |
---|
[495] | 1194 | sc_signal<uint32_t> r_cleanup_to_ixr_cmd_index; |
---|
[477] | 1195 | sc_signal<uint32_t> r_cleanup_to_ixr_cmd_pktid; |
---|
| 1196 | sc_signal<addr_t> r_cleanup_to_ixr_cmd_nline; |
---|
[331] | 1197 | }; // end class VciMemCache |
---|
| 1198 | |
---|
| 1199 | }} |
---|
| 1200 | |
---|
| 1201 | #endif |
---|
| 1202 | |
---|
| 1203 | // Local Variables: |
---|
| 1204 | // tab-width: 2 |
---|
| 1205 | // c-basic-offset: 2 |
---|
| 1206 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 1207 | // indent-tabs-mode: nil |
---|
| 1208 | // End: |
---|
| 1209 | |
---|
| 1210 | // vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2 |
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| 1211 | |
---|