Changeset 346 for branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache_dspin_coherence.h
- Timestamp:
- Mar 29, 2013, 6:56:36 PM (11 years ago)
- File:
-
- 1 edited
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branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache_dspin_coherence.h
r336 r346 326 326 327 327 // debug variables (for each FSM) 328 size_t m_debug_start_cycle;329 bool m_debug_ok;330 328 bool m_debug_global; 331 329 bool m_debug_tgt_cmd_fsm; … … 379 377 soclib::caba::VciTarget<vci_param> p_vci_tgt; 380 378 soclib::caba::VciInitiator<vci_param> p_vci_ixr; 381 382 379 soclib::caba::DspinInput<33> p_dspin_in; 383 380 soclib::caba::DspinOutput<40> p_dspin_out; … … 385 382 VciMemCache( 386 383 sc_module_name name, // Instance Name 387 const soclib::common::MappingTable &mtp, // Mapping table for primary requets 388 const soclib::common::MappingTable &mtc, // Mapping table for coherence requets 389 const soclib::common::MappingTable &mtx, // Mapping table for XRAM 390 const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator) 391 const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator) 392 const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target) 393 const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup 394 size_t nways, // Number of ways per set 395 size_t nsets, // Number of sets 396 size_t nwords, // Number of words per line 397 size_t heap_size=1024, // Size of the heap 398 size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT 399 size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT 400 size_t debug_start_cycle=0, 401 bool debug_ok=false); 384 const soclib::common::MappingTable &mtp, // Mapping table for direct network 385 const soclib::common::MappingTable &mtx, // Mapping table for external network 386 const soclib::common::IntTab &srcid_x, // global index on external network 387 const soclib::common::IntTab &tgtid_d, // global index on direct network 388 const size_t cc_global_id, // global index on cc network 389 const size_t nways, // Number of ways per set 390 const size_t nsets, // Number of sets 391 const size_t nwords, // Number of words per line 392 const size_t max_copies, // max number of copies in heap 393 const size_t heap_size=1024, // number of heap entries 394 const size_t trt_lines=TRANSACTION_TAB_LINES, 395 const size_t upt_lines=UPDATE_TAB_LINES, 396 const size_t debug_start_cycle=0, 397 const bool debug_ok=false ); 402 398 403 399 ~VciMemCache(); … … 417 413 418 414 // Component attributes 419 std::list<soclib::common::Segment> m_seglist; // memory cached into the cache 420 std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache 421 422 const size_t m_initiators; // Number of initiators 423 const size_t m_heap_size; // Size of the heap 424 const size_t m_ways; // Number of ways in a set 425 const size_t m_sets; // Number of cache sets 426 const size_t m_words; // Number of words in a line 427 const size_t m_srcid_ixr; // Srcid for requests to XRAM 428 const size_t m_srcid_ini; // Srcid for requests to processors 429 430 uint32_t m_transaction_tab_lines; 431 TransactionTab m_transaction_tab; // xram transaction table 432 uint32_t m_update_tab_lines; 433 UpdateTab m_update_tab; // pending update & invalidate 434 CacheDirectory m_cache_directory; // data cache directory 435 CacheData m_cache_data; // data array[set][way][word] 436 HeapDirectory m_heap; // heap for copies 415 std::list<soclib::common::Segment> m_seglist; // segments allocated to memcache 416 size_t m_nseg; // number of segments 417 soclib::common::Segment **m_seg; // array of segments pointers 418 const size_t m_srcid_x; // global index on external network 419 const size_t m_initiators; // Number of initiators 420 const size_t m_heap_size; // Size of the heap 421 const size_t m_ways; // Number of ways in a set 422 const size_t m_sets; // Number of cache sets 423 const size_t m_words; // Number of words in a line 424 const size_t m_cc_global_id; // global_index on cc network 425 size_t m_debug_start_cycle; 426 bool m_debug_ok; 427 uint32_t m_trt_lines; 428 TransactionTab m_trt; // xram transaction table 429 uint32_t m_upt_lines; 430 UpdateTab m_upt; // pending update & invalidate 431 CacheDirectory m_cache_directory; // data cache directory 432 CacheData m_cache_data; // data array[set][way][word] 433 HeapDirectory m_heap; // heap for copies 434 size_t m_max_copies; // max number of copies in heap 437 435 GenericLLSCGlobalTable 438 < 439 32 , // desired number of slots 440 4096, // number of processors in the system 441 8000, // registratioçn life span (in # of LL operations) 442 typename vci_param::fast_addr_t // address type 443 > 444 m_llsc_table; // ll/sc global registration table 436 < 32 , // number of slots 437 4096, // number of processors in the system 438 8000, // registratioçn life span (in # of LL operations) 439 typename vci_param::fast_addr_t > // address type 440 m_llsc_table; // ll/sc global registration table 445 441 446 442 // adress masks 447 const soclib::common::AddressMaskingTable<vci_addr_t> m_x;448 const soclib::common::AddressMaskingTable<vci_addr_t> m_y;449 const soclib::common::AddressMaskingTable<vci_addr_t> m_z;450 const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;443 const soclib::common::AddressMaskingTable<vci_addr_t> m_x; 444 const soclib::common::AddressMaskingTable<vci_addr_t> m_y; 445 const soclib::common::AddressMaskingTable<vci_addr_t> m_z; 446 const soclib::common::AddressMaskingTable<vci_addr_t> m_nline; 451 447 452 448 // broadcast address 453 uint32_t m_broadcast_address; 454 455 ////////////////////////////////////////////////// 456 // Others registers 457 ////////////////////////////////////////////////// 458 sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line 459 sc_signal<size_t> xxx_count; 449 uint32_t m_broadcast_address; 460 450 461 451 ////////////////////////////////////////////////// … … 495 485 sc_signal<int> r_tgt_cmd_fsm; 496 486 497 size_t m_nseg;498 size_t m_ncseg;499 soclib::common::Segment **m_seg;500 soclib::common::Segment **m_cseg;501 487 /////////////////////////////////////////////////////// 502 488 // Registers controlled by the READ fsm
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