[747] | 1 | /////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: top.cpp (for tsar_generic_iob platform) |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : august 2013 |
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| 6 | // This program is released under the GNU public license |
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| 7 | /////////////////////////////////////////////////////////////////////////////// |
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| 8 | // This file define a generic TSAR architecture with an IO network emulating |
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| 9 | // an external bus (i.e. Hypertransport) to access 7 external peripherals: |
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| 10 | // |
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| 11 | // - FBUF : Frame Buffer |
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| 12 | // - MTTY : multi TTY (one channel) |
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| 13 | // - MNIC : Network controller (up to 2 channels) |
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| 14 | // - CDMA : Chained Buffer DMA controller (up to 4 channels) |
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| 15 | // - BDEV : Dlock Device controler (one channel) |
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| 16 | // - IOPI : HWI to SWI translator. |
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| 17 | // |
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| 18 | // The internal physical address space is 40 bits, and the cluster index |
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| 19 | // is defined by the 8 MSB bits, using a fixed format: X is encoded on 4 bits, |
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| 20 | // Y is encodes on 4 bits, whatever the actual mesh size. |
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| 21 | // => at most 16 * 16 clusters. Each cluster contains up to 4 processors. |
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| 22 | // |
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| 23 | // It contains 3 networks: |
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| 24 | // |
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| 25 | // 1) the "INT" network supports Read/Write transactions |
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| 26 | // between processors and L2 caches or peripherals. |
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| 27 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) |
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| 28 | // It supports also coherence transactions between L1 & L2 caches. |
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| 29 | // 3) the "RAM" network emulates the 3D network between L2 caches |
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| 30 | // and L3 caches, and is implemented as a 2D mesh between the L2 caches, |
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| 31 | // the two IO bridges and the physical RAMs disributed in all clusters. |
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| 32 | // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) |
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| 33 | // 4) the IOX network connects the two IO bridge components to the |
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| 34 | // 7 external peripheral controllers. |
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| 35 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) |
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| 36 | // |
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| 37 | // The external peripherals HWI IRQs are translated to WTI IRQs by the |
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| 38 | // external IOPIC component, that must be configured by the OS to route |
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| 39 | // these WTI ITQS to one or several internal XICU components. |
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| 40 | // - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0] |
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| 41 | // - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0] |
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| 42 | // - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]] |
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| 43 | // - IOPIC HWI[8] connected to IRQ_BDEV |
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| 44 | // - IOPIC HWI[9] connected to IRQ_TTY_RX[0] |
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[748] | 45 | // - IOPIC HWI[31:9] unused (grounded) |
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[747] | 46 | // |
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| 47 | // Besides the external peripherals, each cluster contains one XICU component, |
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| 48 | // and one multi channels DMA component. |
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| 49 | // The XICU component is mainly used to handle WTI IRQs, as only 5 HWI IRQs |
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| 50 | // are connected to XICU in each cluster: |
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| 51 | // - IRQ_IN[0] : MMC |
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| 52 | // - IRQ_IN[1] : DMA channel 0 |
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| 53 | // - IRQ_IN[2] : DMA channel 1 |
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| 54 | // - IRQ_IN[3] : DMA channel 2 |
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| 55 | // - IRQ_IN[4] : DMA channel 3 |
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| 56 | // |
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[855] | 57 | // All clusters are identical, but cluster(0, 0) and cluster(X_SIZE-1, Y_SIZE-1) |
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[747] | 58 | // contain an extra IO bridge component. These IOB0 & IOB1 components are |
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| 59 | // connected to the three networks (INT, RAM, IOX). |
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| 60 | // |
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| 61 | // - It uses two dspin_local_crossbar per cluster to implement the |
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| 62 | // local interconnect correponding to the INT network. |
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| 63 | // - It uses three dspin_local_crossbar per cluster to implement the |
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| 64 | // local interconnect correponding to the coherence INT network. |
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| 65 | // - It uses two virtual_dspin_router per cluster to implement |
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| 66 | // the INT network (routing both the direct and coherence trafic). |
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| 67 | // - It uses two dspin_router per cluster to implement the RAM network. |
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| 68 | // - It uses the vci_cc_vcache_wrapper. |
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| 69 | // - It uses the vci_mem_cache. |
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| 70 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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| 71 | // - It contains one vci_simple ram per cluster to model the L3 cache. |
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| 72 | // |
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| 73 | // The TsarIobCluster component is defined in files |
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| 74 | // tsar_iob_cluster.* (with * = cpp, h, sd) |
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| 75 | // |
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| 76 | // The main hardware parameters must be defined in the hard_config.h file : |
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| 77 | // - X_SIZE : number of clusters in a row |
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| 78 | // - Y_SIZE : number of clusters in a column |
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| 79 | // - NB_PROCS_MAX : number of processors per cluster (power of 2) |
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| 80 | // - NB_TTY_CHANNELS : number of TTY channels in I/O network (must be 1) |
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| 81 | // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 2) |
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| 82 | // - NB_CMA_CHANNELS : number of CMA channels in I/O network (up to 4) |
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| 83 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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| 84 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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| 85 | // - XCU_NB_INPUTS : number of HWIs = number of WTIs = number of PTIs |
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| 86 | // |
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| 87 | // Some secondary hardware parameters must be defined in this top.cpp file: |
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| 88 | // - XRAM_LATENCY : external ram latency |
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| 89 | // - MEMC_WAYS : L2 cache number of ways |
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| 90 | // - MEMC_SETS : L2 cache number of sets |
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| 91 | // - L1_IWAYS |
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| 92 | // - L1_ISETS |
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| 93 | // - L1_DWAYS |
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| 94 | // - L1_DSETS |
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| 95 | // - BDEV_IMAGE_NAME : file pathname for block device |
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| 96 | // - NIC_RX_NAME : file pathname for NIC received packets |
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| 97 | // - NIC_TX_NAME : file pathname for NIC transmited packets |
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| 98 | // - NIC_TIMEOUT : max number of cycles before closing a container |
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| 99 | // |
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| 100 | // General policy for 40 bits physical address decoding: |
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| 101 | // All physical segments base addresses are multiple of 1 Mbytes |
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| 102 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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[806] | 103 | // The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define |
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[747] | 104 | // the cluster index, and the LADR bits define the local index: |
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| 105 | // |X_ID|Y_ID| LADR | OFFSET | |
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| 106 | // | 4 | 4 | 8 | 24 | |
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| 107 | // |
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| 108 | // General policy for 14 bits SRCID decoding: |
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| 109 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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| 110 | // |X_ID|Y_ID| L_ID | |
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| 111 | // | 4 | 4 | 6 | |
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| 112 | ///////////////////////////////////////////////////////////////////////// |
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| 113 | |
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| 114 | #include <systemc> |
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| 115 | #include <sys/time.h> |
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| 116 | #include <iostream> |
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| 117 | #include <sstream> |
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| 118 | #include <cstdlib> |
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| 119 | #include <cstdarg> |
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[750] | 120 | #include <climits> |
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[747] | 121 | #include <stdint.h> |
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| 122 | |
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| 123 | #include "gdbserver.h" |
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| 124 | #include "mapping_table.h" |
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| 125 | |
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| 126 | #include "tsar_iob_cluster.h" |
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| 127 | #include "vci_chbuf_dma.h" |
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| 128 | #include "vci_multi_tty.h" |
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| 129 | #include "vci_multi_nic.h" |
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| 130 | #include "vci_simple_rom.h" |
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| 131 | #include "vci_block_device_tsar.h" |
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| 132 | #include "vci_framebuffer.h" |
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| 133 | #include "vci_iox_network.h" |
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| 134 | #include "vci_iox_network.h" |
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| 135 | #include "vci_iopic.h" |
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[769] | 136 | #include "vci_simhelper.h" |
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[747] | 137 | |
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| 138 | #include "alloc_elems.h" |
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| 139 | |
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| 140 | /////////////////////////////////////////////////// |
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| 141 | // OS |
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| 142 | /////////////////////////////////////////////////// |
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| 143 | #define USE_ALMOS 0 |
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| 144 | |
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| 145 | #define almos_bootloader_pathname "bootloader.bin" |
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| 146 | #define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" |
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| 147 | #define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" |
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| 148 | |
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| 149 | /////////////////////////////////////////////////// |
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| 150 | // Parallelisation |
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| 151 | /////////////////////////////////////////////////// |
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| 152 | #if USE_OPENMP |
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| 153 | #include <omp.h> |
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| 154 | #endif |
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| 155 | |
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| 156 | /////////////////////////////////////////////////////////// |
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| 157 | // DSPIN parameters |
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| 158 | /////////////////////////////////////////////////////////// |
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| 159 | |
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| 160 | #define dspin_int_cmd_width 39 |
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| 161 | #define dspin_int_rsp_width 32 |
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| 162 | |
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| 163 | #define dspin_ram_cmd_width 64 |
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| 164 | #define dspin_ram_rsp_width 64 |
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| 165 | |
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| 166 | /////////////////////////////////////////////////////////// |
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| 167 | // VCI fields width for the 3 VCI networks |
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| 168 | /////////////////////////////////////////////////////////// |
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| 169 | |
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| 170 | #define vci_cell_width_int 4 |
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| 171 | #define vci_cell_width_ext 8 |
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| 172 | |
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| 173 | #define vci_plen_width 8 |
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| 174 | #define vci_address_width 40 |
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| 175 | #define vci_rerror_width 1 |
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| 176 | #define vci_clen_width 1 |
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| 177 | #define vci_rflag_width 1 |
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| 178 | #define vci_srcid_width 14 |
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| 179 | #define vci_pktid_width 4 |
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| 180 | #define vci_trdid_width 4 |
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| 181 | #define vci_wrplen_width 1 |
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| 182 | |
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| 183 | //////////////////////////////////////////////////////////// |
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| 184 | // Main Hardware Parameters values |
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| 185 | //////////////////////i///////////////////////////////////// |
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| 186 | |
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| 187 | #include "hard_config.h" |
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| 188 | |
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| 189 | //////////////////////////////////////////////////////////// |
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| 190 | // Secondary Hardware Parameters values |
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| 191 | //////////////////////i///////////////////////////////////// |
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| 192 | |
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| 193 | #define XRAM_LATENCY 0 |
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| 194 | |
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| 195 | #define MEMC_WAYS 16 |
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| 196 | #define MEMC_SETS 256 |
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| 197 | |
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| 198 | #define L1_IWAYS 4 |
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| 199 | #define L1_ISETS 64 |
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| 200 | |
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| 201 | #define L1_DWAYS 4 |
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| 202 | #define L1_DSETS 64 |
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| 203 | |
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| 204 | #define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" |
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| 205 | |
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[760] | 206 | #define NIC_RX_NAME "/dev/null" |
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| 207 | #define NIC_TX_NAME "/dev/null" |
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[747] | 208 | #define NIC_TIMEOUT 10000 |
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| 209 | |
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| 210 | #define NORTH 0 |
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| 211 | #define SOUTH 1 |
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| 212 | #define EAST 2 |
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| 213 | #define WEST 3 |
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| 214 | |
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[855] | 215 | #define cluster(x, y) ((y) + ((x) << Y_WIDTH)) |
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[747] | 216 | |
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| 217 | //////////////////////////////////////////////////////////// |
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| 218 | // Software to be loaded in ROM & RAM |
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| 219 | //////////////////////i///////////////////////////////////// |
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| 220 | |
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| 221 | #define BOOT_SOFT_NAME "../../softs/tsar_boot/preloader.elf" |
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| 222 | |
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| 223 | //////////////////////////////////////////////////////////// |
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| 224 | // DEBUG Parameters default values |
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| 225 | //////////////////////i///////////////////////////////////// |
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| 226 | |
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[748] | 227 | #define MAX_FROZEN_CYCLES 200000 |
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[747] | 228 | |
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| 229 | ///////////////////////////////////////////////////////// |
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| 230 | // Physical segments definition |
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| 231 | ///////////////////////////////////////////////////////// |
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| 232 | |
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| 233 | // All physical segments base addresses and sizes are defined |
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| 234 | // in the hard_config.h file. For replicated segments, the |
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| 235 | // base address is incremented by a cluster offset: |
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[855] | 236 | // offset = cluster(x, y) << (address_width-X_WIDTH-Y_WIDTH); |
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[747] | 237 | |
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| 238 | //////////////////////////////////////////////////////////////////////// |
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| 239 | // SRCID definition |
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| 240 | //////////////////////////////////////////////////////////////////////// |
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| 241 | // All initiators are in the same indexing space (14 bits). |
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| 242 | // The SRCID is structured in two fields: |
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| 243 | // - The 10 MSB bits define the cluster index (left aligned) |
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| 244 | // - The 4 LSB bits define the local index. |
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| 245 | // Two different initiators cannot have the same SRCID, but a given |
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| 246 | // initiator can have two alias SRCIDs: |
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| 247 | // - Internal initiators (procs, mdma) are replicated in all clusters, |
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| 248 | // and each initiator has one single SRCID. |
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| 249 | // - External initiators (bdev, cdma) are not replicated, but can be |
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| 250 | // accessed in 2 clusters : cluster_iob0 and cluster_iob1. |
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| 251 | // They have the same local index, but two different cluster indexes. |
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| 252 | // |
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| 253 | // As cluster_iob0 and cluster_iob1 contain both internal initiators |
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| 254 | // and external initiators, they must have different local indexes. |
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| 255 | // Consequence: For a local interconnect, the INI_ID port index |
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| 256 | // is NOT equal to the SRCID local index, and the local interconnect |
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| 257 | // must make a translation: SRCID => INI_ID |
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| 258 | //////////////////////////////////////////////////////////////////////// |
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| 259 | |
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| 260 | #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 |
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| 261 | #define MDMA_LOCAL_SRCID 0x8 |
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| 262 | #define IOBX_LOCAL_SRCID 0x9 |
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| 263 | #define MEMC_LOCAL_SRCID 0xA |
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| 264 | #define CDMA_LOCAL_SRCID 0xB |
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| 265 | #define BDEV_LOCAL_SRCID 0xC |
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| 266 | #define IOPI_LOCAL_SRCID 0xD |
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| 267 | |
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| 268 | /////////////////////////////////////////////////////////////////////// |
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| 269 | // TGT_ID and INI_ID port indexing for INT local interconnect |
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| 270 | /////////////////////////////////////////////////////////////////////// |
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| 271 | |
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| 272 | #define INT_MEMC_TGT_ID 0 |
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| 273 | #define INT_XICU_TGT_ID 1 |
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| 274 | #define INT_MDMA_TGT_ID 2 |
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[748] | 275 | #define INT_BROM_TGT_ID 3 |
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| 276 | #define INT_IOBX_TGT_ID 4 |
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[747] | 277 | |
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| 278 | #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) |
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| 279 | #define INT_MDMA_INI_ID (NB_PROCS_MAX) |
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| 280 | #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) |
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| 281 | |
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| 282 | /////////////////////////////////////////////////////////////////////// |
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| 283 | // TGT_ID and INI_ID port indexing for RAM local interconnect |
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| 284 | /////////////////////////////////////////////////////////////////////// |
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| 285 | |
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| 286 | #define RAM_XRAM_TGT_ID 0 |
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| 287 | |
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| 288 | #define RAM_MEMC_INI_ID 0 |
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| 289 | #define RAM_IOBX_INI_ID 1 |
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| 290 | |
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| 291 | /////////////////////////////////////////////////////////////////////// |
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| 292 | // TGT_ID and INI_ID port indexing for I0X local interconnect |
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| 293 | /////////////////////////////////////////////////////////////////////// |
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| 294 | |
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| 295 | #define IOX_FBUF_TGT_ID 0 |
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| 296 | #define IOX_BDEV_TGT_ID 1 |
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| 297 | #define IOX_MNIC_TGT_ID 2 |
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| 298 | #define IOX_CDMA_TGT_ID 3 |
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[748] | 299 | #define IOX_MTTY_TGT_ID 4 |
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| 300 | #define IOX_IOPI_TGT_ID 5 |
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[769] | 301 | #define IOX_SIMH_TGT_ID 6 |
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| 302 | #define IOX_IOB0_TGT_ID 7 |
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| 303 | #define IOX_IOB1_TGT_ID 8 |
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[747] | 304 | |
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| 305 | #define IOX_BDEV_INI_ID 0 |
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| 306 | #define IOX_CDMA_INI_ID 1 |
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| 307 | #define IOX_IOPI_INI_ID 2 |
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| 308 | #define IOX_IOB0_INI_ID 3 |
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| 309 | #define IOX_IOB1_INI_ID 4 |
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| 310 | |
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| 311 | //////////////////////////////////////////////////////////////////////// |
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| 312 | int _main(int argc, char *argv[]) |
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| 313 | //////////////////////////////////////////////////////////////////////// |
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| 314 | { |
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| 315 | using namespace sc_core; |
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| 316 | using namespace soclib::caba; |
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| 317 | using namespace soclib::common; |
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| 318 | |
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| 319 | |
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[855] | 320 | char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code |
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| 321 | size_t ncycles = UINT_MAX; // simulated cycles |
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| 322 | char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image |
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| 323 | char nic_rx_name[256] = NIC_RX_NAME; // pathname: rx packets file |
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| 324 | char nic_tx_name[256] = NIC_TX_NAME; // pathname: tx packets file |
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| 325 | ssize_t threads_nr = 1; // simulator's threads number |
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| 326 | size_t faulty_router_id = 0xFFFFFFFF; // faulty router coordinates |
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| 327 | bool debug_ok = false; // trace activated |
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| 328 | size_t debug_period = 1; // trace period |
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| 329 | size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc |
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| 330 | size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc |
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| 331 | size_t debug_xram_id = 0xFFFFFFFF; // index of traced xram |
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| 332 | bool debug_iob = false; // trace iob0 & iob1 when true |
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| 333 | uint32_t debug_from = 0; // trace start cycle |
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| 334 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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| 335 | size_t cluster_iob0 = cluster(0, 0); // cluster containing IOB0 |
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| 336 | size_t cluster_iob1 = cluster(X_SIZE-1, Y_SIZE-1); // cluster containing IOB1 |
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[747] | 337 | |
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| 338 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
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| 339 | "ERROR: we must have X_WIDTH == Y_WIDTH == 4"); |
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| 340 | |
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| 341 | ////////////// command line arguments ////////////////////// |
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| 342 | if (argc > 1) |
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| 343 | { |
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| 344 | for (int n = 1; n < argc; n = n + 2) |
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| 345 | { |
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[855] | 346 | if ((strcmp(argv[n], "-NCYCLES") == 0) && (n+1<argc)) |
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[747] | 347 | { |
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[748] | 348 | ncycles = strtol(argv[n+1], NULL, 0); |
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[747] | 349 | } |
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[855] | 350 | else if ((strcmp(argv[n], "-SOFT") == 0) && (n+1<argc) ) |
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[747] | 351 | { |
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| 352 | strcpy(soft_name, argv[n+1]); |
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| 353 | } |
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[855] | 354 | else if ((strcmp(argv[n], "-DEBUG") == 0) && (n+1<argc) ) |
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[747] | 355 | { |
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| 356 | debug_ok = true; |
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[748] | 357 | debug_from = strtol(argv[n+1], NULL, 0); |
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[747] | 358 | } |
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[855] | 359 | else if ((strcmp(argv[n], "-DISK") == 0) && (n+1<argc) ) |
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[747] | 360 | { |
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| 361 | strcpy(disk_name, argv[n+1]); |
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| 362 | } |
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[855] | 363 | else if ((strcmp(argv[n], "-MEMCID") == 0) && (n+1<argc) ) |
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[747] | 364 | { |
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[748] | 365 | debug_memc_id = strtol(argv[n+1], NULL, 0); |
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[855] | 366 | size_t x = debug_memc_id >> Y_WIDTH; |
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| 367 | size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); |
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[806] | 368 | if( (x>=X_SIZE) || (y>=Y_SIZE) ) |
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[747] | 369 | { |
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[806] | 370 | std::cout << "MEMCID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; |
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[747] | 371 | exit(0); |
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| 372 | } |
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| 373 | } |
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[855] | 374 | else if ((strcmp(argv[n], "-XRAMID") == 0) && (n+1<argc) ) |
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[747] | 375 | { |
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[748] | 376 | debug_xram_id = strtol(argv[n+1], NULL, 0); |
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[855] | 377 | size_t x = debug_xram_id >> Y_WIDTH; |
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| 378 | size_t y = debug_xram_id & ((1 << Y_WIDTH) - 1); |
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[806] | 379 | if( (x>=X_SIZE) || (y>=Y_SIZE) ) |
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[747] | 380 | { |
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[806] | 381 | std::cout << "XRAMID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; |
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[747] | 382 | exit(0); |
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| 383 | } |
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| 384 | } |
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[855] | 385 | else if ((strcmp(argv[n], "-IOB") == 0) && (n+1<argc) ) |
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[747] | 386 | { |
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[748] | 387 | debug_iob = strtol(argv[n+1], NULL, 0); |
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[747] | 388 | } |
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[855] | 389 | else if ((strcmp(argv[n], "-PROCID") == 0) && (n+1<argc) ) |
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[747] | 390 | { |
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[748] | 391 | debug_proc_id = strtol(argv[n+1], NULL, 0); |
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[855] | 392 | size_t cluster_xy = debug_proc_id >> P_WIDTH; |
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| 393 | size_t x = cluster_xy >> Y_WIDTH; |
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| 394 | size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); |
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[806] | 395 | if( (x>=X_SIZE) || (y>=Y_SIZE) ) |
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[747] | 396 | { |
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[806] | 397 | std::cout << "PROCID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; |
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[747] | 398 | exit(0); |
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| 399 | } |
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| 400 | } |
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| 401 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) |
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| 402 | { |
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[748] | 403 | threads_nr = strtol(argv[n+1], NULL, 0); |
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[747] | 404 | threads_nr = (threads_nr < 1) ? 1 : threads_nr; |
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| 405 | } |
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| 406 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
---|
| 407 | { |
---|
[748] | 408 | frozen_cycles = strtol(argv[n+1], NULL, 0); |
---|
[747] | 409 | } |
---|
| 410 | else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) |
---|
| 411 | { |
---|
[748] | 412 | debug_period = strtol(argv[n+1], NULL, 0); |
---|
[747] | 413 | } |
---|
[855] | 414 | else if ((strcmp(argv[n], "-FAULTY_ROUTER") == 0) && (n+1 < argc) ) |
---|
| 415 | { |
---|
| 416 | faulty_router_id = strtol(argv[n+1], NULL, 0); |
---|
| 417 | size_t x = faulty_router_id >> Y_WIDTH; |
---|
| 418 | size_t y = faulty_router_id & ((1 << Y_WIDTH) - 1); |
---|
| 419 | if( (x>=X_SIZE) || (y>=Y_SIZE) ) |
---|
| 420 | { |
---|
| 421 | std::cout << "FAULTY_ROUTER parameter doesn't fit X_SIZE/Y_SIZE" << std::endl; |
---|
| 422 | exit(0); |
---|
| 423 | } |
---|
| 424 | } |
---|
[747] | 425 | else |
---|
| 426 | { |
---|
[855] | 427 | std::cout << " Arguments are (key, value) couples." << std::endl; |
---|
[747] | 428 | std::cout << " The order is not important." << std::endl; |
---|
| 429 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
---|
| 430 | std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; |
---|
| 431 | std::cout << " -DISK pathname_for_disk_image" << std::endl; |
---|
| 432 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
---|
| 433 | std::cout << " -DEBUG debug_start_cycle" << std::endl; |
---|
| 434 | std::cout << " -THREADS simulator's threads number" << std::endl; |
---|
| 435 | std::cout << " -FROZEN max_number_of_lines" << std::endl; |
---|
| 436 | std::cout << " -PERIOD number_of_cycles between trace" << std::endl; |
---|
| 437 | std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; |
---|
| 438 | std::cout << " -XRAMID index_xram_to_be_traced" << std::endl; |
---|
| 439 | std::cout << " -PROCID index_proc_to_be_traced" << std::endl; |
---|
| 440 | std::cout << " -IOB non_zero_value" << std::endl; |
---|
| 441 | exit(0); |
---|
| 442 | } |
---|
| 443 | } |
---|
| 444 | } |
---|
| 445 | |
---|
[748] | 446 | // Activate Distributed Boot (set by environment variable) |
---|
| 447 | // When this is activated, every processor boots with its instruction and data |
---|
| 448 | // physical address extension register initialized to its cluster index |
---|
| 449 | // (X_LOCAL, Y_LOCAL). To support this feature, a distributed ROM is |
---|
| 450 | // implemented in each cluster. |
---|
| 451 | |
---|
| 452 | const bool distributed_boot = (getenv("DISTRIBUTED_BOOT") != NULL); |
---|
| 453 | |
---|
[747] | 454 | // checking hardware parameters |
---|
[806] | 455 | assert( (X_SIZE <= (1 << X_WIDTH)) and |
---|
| 456 | "The X_SIZE parameter cannot be larger than 16" ); |
---|
[747] | 457 | |
---|
[806] | 458 | assert( (Y_SIZE <= (1 << Y_WIDTH)) and |
---|
| 459 | "The Y_SIZE parameter cannot be larger than 16" ); |
---|
[747] | 460 | |
---|
| 461 | assert( (NB_PROCS_MAX <= 8) and |
---|
| 462 | "The NB_PROCS_MAX parameter cannot be larger than 8" ); |
---|
| 463 | |
---|
| 464 | assert( (NB_DMA_CHANNELS <= 4) and |
---|
| 465 | "The NB_DMA_CHANNELS parameter cannot be larger than 4" ); |
---|
| 466 | |
---|
| 467 | assert( (NB_TTY_CHANNELS == 1) and |
---|
| 468 | "The NB_TTY_CHANNELS parameter must be 1" ); |
---|
| 469 | |
---|
| 470 | assert( (NB_NIC_CHANNELS == 2) and |
---|
| 471 | "The NB_NIC_CHANNELS parameter must be 2" ); |
---|
| 472 | |
---|
| 473 | std::cout << std::endl << std::dec |
---|
[806] | 474 | << " - X_SIZE = " << X_SIZE << std::endl |
---|
| 475 | << " - Y_SIZE = " << Y_SIZE << std::endl |
---|
[747] | 476 | << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl |
---|
| 477 | << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl |
---|
| 478 | << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl |
---|
| 479 | << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl |
---|
| 480 | << " - MEMC_WAYS = " << MEMC_WAYS << std::endl |
---|
| 481 | << " - MEMC_SETS = " << MEMC_SETS << std::endl |
---|
| 482 | << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl |
---|
| 483 | << " - MAX_FROZEN = " << frozen_cycles << std::endl |
---|
[748] | 484 | << " - DIST_BOOT = " << distributed_boot << std::endl |
---|
[747] | 485 | << " - DEBUG_PROCID = " << debug_proc_id << std::endl |
---|
| 486 | << " - DEBUG_MEMCID = " << debug_memc_id << std::endl |
---|
| 487 | << " - DEBUG_XRAMID = " << debug_xram_id << std::endl; |
---|
| 488 | |
---|
| 489 | std::cout << std::endl; |
---|
| 490 | |
---|
| 491 | #if USE_OPENMP |
---|
| 492 | omp_set_dynamic(false); |
---|
| 493 | omp_set_num_threads(threads_nr); |
---|
| 494 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
---|
| 495 | #endif |
---|
| 496 | |
---|
| 497 | // Define VciParams objects |
---|
| 498 | typedef soclib::caba::VciParams<vci_cell_width_int, |
---|
| 499 | vci_plen_width, |
---|
| 500 | vci_address_width, |
---|
| 501 | vci_rerror_width, |
---|
| 502 | vci_clen_width, |
---|
| 503 | vci_rflag_width, |
---|
| 504 | vci_srcid_width, |
---|
| 505 | vci_pktid_width, |
---|
| 506 | vci_trdid_width, |
---|
| 507 | vci_wrplen_width> vci_param_int; |
---|
| 508 | |
---|
| 509 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
---|
| 510 | vci_plen_width, |
---|
| 511 | vci_address_width, |
---|
| 512 | vci_rerror_width, |
---|
| 513 | vci_clen_width, |
---|
| 514 | vci_rflag_width, |
---|
| 515 | vci_srcid_width, |
---|
| 516 | vci_pktid_width, |
---|
| 517 | vci_trdid_width, |
---|
| 518 | vci_wrplen_width> vci_param_ext; |
---|
| 519 | |
---|
| 520 | ///////////////////////////////////////////////////////////////////// |
---|
| 521 | // INT network mapping table |
---|
| 522 | // - two levels address decoding for commands |
---|
| 523 | // - two levels srcid decoding for responses |
---|
| 524 | // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster |
---|
| 525 | // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster |
---|
| 526 | ///////////////////////////////////////////////////////////////////// |
---|
| 527 | MappingTable maptab_int( vci_address_width, |
---|
[806] | 528 | IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), |
---|
| 529 | IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), |
---|
[747] | 530 | 0x00FF000000); |
---|
| 531 | |
---|
[806] | 532 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 533 | { |
---|
[806] | 534 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
[747] | 535 | { |
---|
[855] | 536 | uint64_t offset = ((uint64_t)cluster(x, y)) |
---|
[806] | 537 | << (vci_address_width-X_WIDTH-Y_WIDTH); |
---|
[747] | 538 | bool config = true; |
---|
| 539 | bool cacheable = true; |
---|
| 540 | |
---|
| 541 | // the four following segments are defined in all clusters |
---|
| 542 | |
---|
| 543 | std::ostringstream smemc_conf; |
---|
| 544 | smemc_conf << "int_seg_memc_conf_" << x << "_" << y; |
---|
| 545 | maptab_int.add(Segment(smemc_conf.str(), SEG_MMC_BASE+offset, SEG_MMC_SIZE, |
---|
[855] | 546 | IntTab(cluster(x, y), INT_MEMC_TGT_ID), not cacheable, config )); |
---|
[747] | 547 | |
---|
| 548 | std::ostringstream smemc_xram; |
---|
| 549 | smemc_xram << "int_seg_memc_xram_" << x << "_" << y; |
---|
| 550 | maptab_int.add(Segment(smemc_xram.str(), SEG_RAM_BASE+offset, SEG_RAM_SIZE, |
---|
[855] | 551 | IntTab(cluster(x, y), INT_MEMC_TGT_ID), cacheable)); |
---|
[747] | 552 | |
---|
| 553 | std::ostringstream sxicu; |
---|
| 554 | sxicu << "int_seg_xicu_" << x << "_" << y; |
---|
| 555 | maptab_int.add(Segment(sxicu.str(), SEG_XCU_BASE+offset, SEG_XCU_SIZE, |
---|
[855] | 556 | IntTab(cluster(x, y), INT_XICU_TGT_ID), not cacheable)); |
---|
[747] | 557 | |
---|
| 558 | std::ostringstream smdma; |
---|
| 559 | smdma << "int_seg_mdma_" << x << "_" << y; |
---|
| 560 | maptab_int.add(Segment(smdma.str(), SEG_DMA_BASE+offset, SEG_DMA_SIZE, |
---|
[855] | 561 | IntTab(cluster(x, y), INT_MDMA_TGT_ID), not cacheable)); |
---|
[747] | 562 | |
---|
[748] | 563 | std::ostringstream sbrom; |
---|
| 564 | sbrom << "int_seg_brom_" << x << "_" << y; |
---|
| 565 | maptab_int.add(Segment(sbrom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, |
---|
[855] | 566 | IntTab(cluster(x, y), INT_BROM_TGT_ID), cacheable)); |
---|
[748] | 567 | |
---|
[747] | 568 | // the following segments are only defined in cluster_iob0 or in cluster_iob1 |
---|
| 569 | |
---|
[855] | 570 | if ( (cluster(x, y) == cluster_iob0) or (cluster(x, y) == cluster_iob1) ) |
---|
[747] | 571 | { |
---|
| 572 | std::ostringstream siobx; |
---|
| 573 | siobx << "int_seg_iobx_" << x << "_" << y; |
---|
| 574 | maptab_int.add(Segment(siobx.str(), SEG_IOB_BASE+offset, SEG_IOB_SIZE, |
---|
[855] | 575 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable, config )); |
---|
[747] | 576 | |
---|
| 577 | std::ostringstream stty; |
---|
| 578 | stty << "int_seg_mtty_" << x << "_" << y; |
---|
| 579 | maptab_int.add(Segment(stty.str(), SEG_TTY_BASE+offset, SEG_TTY_SIZE, |
---|
[855] | 580 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 581 | |
---|
| 582 | std::ostringstream sfbf; |
---|
| 583 | sfbf << "int_seg_fbuf_" << x << "_" << y; |
---|
| 584 | maptab_int.add(Segment(sfbf.str(), SEG_FBF_BASE+offset, SEG_FBF_SIZE, |
---|
[855] | 585 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 586 | |
---|
| 587 | std::ostringstream sbdv; |
---|
| 588 | sbdv << "int_seg_bdev_" << x << "_" << y; |
---|
| 589 | maptab_int.add(Segment(sbdv.str(), SEG_IOC_BASE+offset, SEG_IOC_SIZE, |
---|
[855] | 590 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 591 | |
---|
| 592 | std::ostringstream snic; |
---|
| 593 | snic << "int_seg_mnic_" << x << "_" << y; |
---|
| 594 | maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, |
---|
[855] | 595 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 596 | |
---|
| 597 | std::ostringstream sdma; |
---|
| 598 | sdma << "int_seg_cdma_" << x << "_" << y; |
---|
| 599 | maptab_int.add(Segment(sdma.str(), SEG_CMA_BASE+offset, SEG_CMA_SIZE, |
---|
[855] | 600 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 601 | |
---|
| 602 | std::ostringstream spic; |
---|
| 603 | spic << "int_seg_iopi_" << x << "_" << y; |
---|
| 604 | maptab_int.add(Segment(spic.str(), SEG_PIC_BASE+offset, SEG_PIC_SIZE, |
---|
[855] | 605 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[769] | 606 | |
---|
| 607 | std::ostringstream ssim; |
---|
| 608 | ssim << "int_seg_simh_" << x << "_" << y; |
---|
| 609 | maptab_int.add(Segment(ssim.str(), SEG_SIM_BASE+offset, SEG_SIM_SIZE, |
---|
[855] | 610 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 611 | } |
---|
| 612 | |
---|
| 613 | // This define the mapping between the SRCIDs |
---|
| 614 | // and the port index on the local interconnect. |
---|
| 615 | |
---|
[855] | 616 | maptab_int.srcid_map( IntTab( cluster(x, y), MDMA_LOCAL_SRCID ), |
---|
| 617 | IntTab( cluster(x, y), INT_MDMA_INI_ID ) ); |
---|
[747] | 618 | |
---|
[855] | 619 | maptab_int.srcid_map( IntTab( cluster(x, y), IOBX_LOCAL_SRCID ), |
---|
| 620 | IntTab( cluster(x, y), INT_IOBX_INI_ID ) ); |
---|
[747] | 621 | |
---|
[855] | 622 | maptab_int.srcid_map( IntTab( cluster(x, y), IOPI_LOCAL_SRCID ), |
---|
| 623 | IntTab( cluster(x, y), INT_IOBX_INI_ID ) ); |
---|
[747] | 624 | |
---|
| 625 | for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) |
---|
[855] | 626 | maptab_int.srcid_map( IntTab( cluster(x, y), PROC_LOCAL_SRCID+p ), |
---|
| 627 | IntTab( cluster(x, y), INT_PROC_INI_ID+p ) ); |
---|
[747] | 628 | } |
---|
| 629 | } |
---|
| 630 | std::cout << "INT network " << maptab_int << std::endl; |
---|
| 631 | |
---|
| 632 | ///////////////////////////////////////////////////////////////////////// |
---|
| 633 | // RAM network mapping table |
---|
| 634 | // - two levels address decoding for commands |
---|
| 635 | // - two levels srcid decoding for responses |
---|
| 636 | // - 2 local initiators (MEMC, IOBX) per cluster |
---|
| 637 | // (IOBX component only in cluster_iob0 and cluster_iob1) |
---|
| 638 | // - 1 local target (XRAM) per cluster |
---|
| 639 | //////////////////////////////////////////////////////////////////////// |
---|
| 640 | MappingTable maptab_ram( vci_address_width, |
---|
[806] | 641 | IntTab(X_WIDTH+Y_WIDTH, 0), |
---|
| 642 | IntTab(X_WIDTH+Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), |
---|
[747] | 643 | 0x00FF000000); |
---|
| 644 | |
---|
[806] | 645 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 646 | { |
---|
[806] | 647 | for (size_t y = 0; y < Y_SIZE ; y++) |
---|
[747] | 648 | { |
---|
[855] | 649 | uint64_t offset = ((uint64_t)cluster(x, y)) |
---|
[806] | 650 | << (vci_address_width-X_WIDTH-Y_WIDTH); |
---|
[747] | 651 | |
---|
| 652 | std::ostringstream sxram; |
---|
| 653 | sxram << "ext_seg_xram_" << x << "_" << y; |
---|
| 654 | maptab_ram.add(Segment(sxram.str(), SEG_RAM_BASE+offset, |
---|
[855] | 655 | SEG_RAM_SIZE, IntTab(cluster(x, y), RAM_XRAM_TGT_ID), false)); |
---|
[747] | 656 | } |
---|
| 657 | } |
---|
| 658 | |
---|
| 659 | // This define the mapping between the initiators SRCID |
---|
| 660 | // and the port index on the RAM local interconnect. |
---|
| 661 | // External initiator have two alias SRCID (iob0 / iob1) |
---|
| 662 | |
---|
| 663 | maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), |
---|
| 664 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 665 | |
---|
| 666 | maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), |
---|
| 667 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 668 | |
---|
| 669 | maptab_ram.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), |
---|
| 670 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 671 | |
---|
| 672 | maptab_ram.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), |
---|
| 673 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 674 | |
---|
| 675 | maptab_ram.srcid_map( IntTab( cluster_iob0, IOPI_LOCAL_SRCID ), |
---|
| 676 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 677 | |
---|
| 678 | maptab_ram.srcid_map( IntTab( cluster_iob1, IOPI_LOCAL_SRCID ), |
---|
| 679 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 680 | |
---|
| 681 | maptab_ram.srcid_map( IntTab( cluster_iob0, MEMC_LOCAL_SRCID ), |
---|
| 682 | IntTab( cluster_iob0, RAM_MEMC_INI_ID ) ); |
---|
| 683 | |
---|
| 684 | maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), |
---|
| 685 | IntTab( cluster_iob1, RAM_MEMC_INI_ID ) ); |
---|
| 686 | |
---|
| 687 | std::cout << "RAM network " << maptab_ram << std::endl; |
---|
| 688 | |
---|
| 689 | /////////////////////////////////////////////////////////////////////// |
---|
| 690 | // IOX network mapping table |
---|
| 691 | // - two levels address decoding for commands (9, 7) bits |
---|
| 692 | // - two levels srcid decoding for responses |
---|
| 693 | // - 5 initiators (IOB0, IOB1, BDEV, CDMA, IOPI) |
---|
| 694 | // - 9 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC, IOPI) |
---|
| 695 | // |
---|
| 696 | // Address bit 32 is used to determine if a command must be routed to |
---|
| 697 | // IOB0 or IOB1. |
---|
| 698 | /////////////////////////////////////////////////////////////////////// |
---|
| 699 | MappingTable maptab_iox( |
---|
| 700 | vci_address_width, |
---|
[806] | 701 | IntTab(X_WIDTH + Y_WIDTH - 1, 16 - X_WIDTH - Y_WIDTH + 1), |
---|
| 702 | IntTab(X_WIDTH + Y_WIDTH , vci_param_ext::S - X_WIDTH - Y_WIDTH), |
---|
[747] | 703 | 0x00FF000000); |
---|
| 704 | |
---|
| 705 | // External peripherals segments |
---|
| 706 | // When there is more than one cluster, external peripherals can be accessed |
---|
| 707 | // through two segments, depending on the used IOB (IOB0 or IOB1). |
---|
| 708 | |
---|
| 709 | const uint64_t iob0_base = ((uint64_t)cluster_iob0) |
---|
[806] | 710 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[747] | 711 | |
---|
| 712 | maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TTY_BASE + iob0_base, SEG_TTY_SIZE, |
---|
| 713 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
| 714 | maptab_iox.add(Segment("iox_seg_fbuf_0", SEG_FBF_BASE + iob0_base, SEG_FBF_SIZE, |
---|
| 715 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
| 716 | maptab_iox.add(Segment("iox_seg_bdev_0", SEG_IOC_BASE + iob0_base, SEG_IOC_SIZE, |
---|
| 717 | IntTab(0, IOX_BDEV_TGT_ID), false)); |
---|
| 718 | maptab_iox.add(Segment("iox_seg_mnic_0", SEG_NIC_BASE + iob0_base, SEG_NIC_SIZE, |
---|
| 719 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
| 720 | maptab_iox.add(Segment("iox_seg_cdma_0", SEG_CMA_BASE + iob0_base, SEG_CMA_SIZE, |
---|
| 721 | IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
| 722 | maptab_iox.add(Segment("iox_seg_iopi_0", SEG_PIC_BASE + iob0_base, SEG_PIC_SIZE, |
---|
| 723 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
[769] | 724 | maptab_iox.add(Segment("iox_seg_simh_0", SEG_SIM_BASE + iob0_base, SEG_SIM_SIZE, |
---|
| 725 | IntTab(0, IOX_SIMH_TGT_ID), false)); |
---|
[747] | 726 | |
---|
| 727 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 728 | { |
---|
| 729 | const uint64_t iob1_base = ((uint64_t)cluster_iob1) |
---|
[806] | 730 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[747] | 731 | |
---|
| 732 | maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TTY_BASE + iob1_base, SEG_TTY_SIZE, |
---|
| 733 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
| 734 | maptab_iox.add(Segment("iox_seg_fbuf_1", SEG_FBF_BASE + iob1_base, SEG_FBF_SIZE, |
---|
| 735 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
| 736 | maptab_iox.add(Segment("iox_seg_bdev_1", SEG_IOC_BASE + iob1_base, SEG_IOC_SIZE, |
---|
| 737 | IntTab(0, IOX_BDEV_TGT_ID), false)); |
---|
| 738 | maptab_iox.add(Segment("iox_seg_mnic_1", SEG_NIC_BASE + iob1_base, SEG_NIC_SIZE, |
---|
| 739 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
| 740 | maptab_iox.add(Segment("iox_seg_cdma_1", SEG_CMA_BASE + iob1_base, SEG_CMA_SIZE, |
---|
| 741 | IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
| 742 | maptab_iox.add(Segment("iox_seg_iopi_1", SEG_PIC_BASE + iob1_base, SEG_PIC_SIZE, |
---|
| 743 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
[769] | 744 | maptab_iox.add(Segment("iox_seg_simh_1", SEG_SIM_BASE + iob1_base, SEG_SIM_SIZE, |
---|
| 745 | IntTab(0, IOX_SIMH_TGT_ID), false)); |
---|
[747] | 746 | } |
---|
| 747 | |
---|
| 748 | // If there is more than one cluster, external peripherals |
---|
| 749 | // can access RAM through two segments (IOB0 / IOB1). |
---|
| 750 | // As IOMMU is not activated, addresses are 40 bits (physical addresses), |
---|
| 751 | // and the choice depends on address bit A[32]. |
---|
[806] | 752 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 753 | { |
---|
[806] | 754 | for (size_t y = 0; y < Y_SIZE ; y++) |
---|
[747] | 755 | { |
---|
| 756 | const bool wti = true; |
---|
| 757 | const bool cacheable = true; |
---|
| 758 | |
---|
[855] | 759 | const uint64_t offset = ((uint64_t)cluster(x, y)) |
---|
[806] | 760 | << (vci_address_width-X_WIDTH-Y_WIDTH); |
---|
[747] | 761 | |
---|
| 762 | const uint64_t xicu_base = SEG_XCU_BASE + offset; |
---|
| 763 | |
---|
| 764 | if ( (y & 0x1) == 0 ) // use IOB0 |
---|
| 765 | { |
---|
| 766 | std::ostringstream sxcu0; |
---|
| 767 | sxcu0 << "iox_seg_xcu0_" << x << "_" << y; |
---|
| 768 | maptab_iox.add(Segment(sxcu0.str(), xicu_base, SEG_XCU_SIZE, |
---|
| 769 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, wti)); |
---|
| 770 | |
---|
| 771 | std::ostringstream siob0; |
---|
| 772 | siob0 << "iox_seg_ram0_" << x << "_" << y; |
---|
| 773 | maptab_iox.add(Segment(siob0.str(), offset, SEG_XCU_BASE, |
---|
| 774 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not wti)); |
---|
| 775 | } |
---|
| 776 | else // USE IOB1 |
---|
| 777 | { |
---|
| 778 | std::ostringstream sxcu1; |
---|
| 779 | sxcu1 << "iox_seg_xcu1_" << x << "_" << y; |
---|
| 780 | maptab_iox.add(Segment(sxcu1.str(), xicu_base, SEG_XCU_SIZE, |
---|
| 781 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, wti)); |
---|
| 782 | |
---|
| 783 | std::ostringstream siob1; |
---|
| 784 | siob1 << "iox_seg_ram1_" << x << "_" << y; |
---|
| 785 | maptab_iox.add(Segment(siob1.str(), offset, SEG_XCU_BASE, |
---|
| 786 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not wti)); |
---|
| 787 | } |
---|
| 788 | } |
---|
| 789 | } |
---|
| 790 | |
---|
| 791 | // This define the mapping between the external initiators (SRCID) |
---|
| 792 | // and the port index on the IOX local interconnect. |
---|
| 793 | |
---|
| 794 | maptab_iox.srcid_map( IntTab( 0, CDMA_LOCAL_SRCID ) , |
---|
| 795 | IntTab( 0, IOX_CDMA_INI_ID ) ); |
---|
| 796 | maptab_iox.srcid_map( IntTab( 0, BDEV_LOCAL_SRCID ) , |
---|
| 797 | IntTab( 0, IOX_BDEV_INI_ID ) ); |
---|
| 798 | maptab_iox.srcid_map( IntTab( 0, IOPI_LOCAL_SRCID ) , |
---|
| 799 | IntTab( 0, IOX_IOPI_INI_ID ) ); |
---|
| 800 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB0_INI_ID ) , |
---|
| 801 | IntTab( 0, IOX_IOB0_INI_ID ) ); |
---|
| 802 | |
---|
| 803 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 804 | { |
---|
| 805 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB1_INI_ID ) , |
---|
| 806 | IntTab( 0, IOX_IOB1_INI_ID ) ); |
---|
| 807 | } |
---|
| 808 | |
---|
| 809 | std::cout << "IOX network " << maptab_iox << std::endl; |
---|
| 810 | |
---|
| 811 | //////////////////// |
---|
| 812 | // Signals |
---|
| 813 | /////////////////// |
---|
| 814 | |
---|
| 815 | sc_clock signal_clk("clk"); |
---|
| 816 | sc_signal<bool> signal_resetn("resetn"); |
---|
| 817 | |
---|
| 818 | sc_signal<bool> signal_irq_false; |
---|
| 819 | sc_signal<bool> signal_irq_bdev; |
---|
| 820 | sc_signal<bool> signal_irq_mtty_rx; |
---|
| 821 | sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; |
---|
| 822 | sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; |
---|
| 823 | sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS]; |
---|
| 824 | |
---|
| 825 | // VCI signals for IOX network |
---|
| 826 | VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); |
---|
| 827 | VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); |
---|
| 828 | VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev"); |
---|
| 829 | VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma"); |
---|
| 830 | VciSignals<vci_param_ext> signal_vci_ini_iopi("signal_vci_ini_iopi"); |
---|
| 831 | |
---|
| 832 | VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); |
---|
| 833 | VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); |
---|
| 834 | VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
---|
| 835 | VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
---|
| 836 | VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
---|
| 837 | VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev"); |
---|
| 838 | VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); |
---|
| 839 | VciSignals<vci_param_ext> signal_vci_tgt_iopi("signal_vci_ini_iopi"); |
---|
[769] | 840 | VciSignals<vci_param_ext> signal_vci_tgt_simh("signal_vci_ini_simh"); |
---|
[747] | 841 | |
---|
| 842 | // Horizontal inter-clusters INT network DSPIN |
---|
| 843 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc = |
---|
[806] | 844 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", X_SIZE-1, Y_SIZE, 3); |
---|
[747] | 845 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec = |
---|
[806] | 846 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", X_SIZE-1, Y_SIZE, 3); |
---|
[747] | 847 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc = |
---|
[806] | 848 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", X_SIZE-1, Y_SIZE, 2); |
---|
[747] | 849 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_dec = |
---|
[806] | 850 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_dec", X_SIZE-1, Y_SIZE, 2); |
---|
[747] | 851 | |
---|
| 852 | // Vertical inter-clusters INT network DSPIN |
---|
| 853 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc = |
---|
[806] | 854 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", X_SIZE, Y_SIZE-1, 3); |
---|
[747] | 855 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec = |
---|
[806] | 856 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", X_SIZE, Y_SIZE-1, 3); |
---|
[747] | 857 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc = |
---|
[806] | 858 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", X_SIZE, Y_SIZE-1, 2); |
---|
[747] | 859 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_dec = |
---|
[806] | 860 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_dec", X_SIZE, Y_SIZE-1, 2); |
---|
[747] | 861 | |
---|
| 862 | // Mesh boundaries INT network DSPIN |
---|
[751] | 863 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in = |
---|
[806] | 864 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", X_SIZE, Y_SIZE, 4, 3); |
---|
[751] | 865 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out = |
---|
[806] | 866 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", X_SIZE, Y_SIZE, 4, 3); |
---|
[751] | 867 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in = |
---|
[806] | 868 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", X_SIZE, Y_SIZE, 4, 2); |
---|
[751] | 869 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out = |
---|
[806] | 870 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", X_SIZE, Y_SIZE, 4, 2); |
---|
[747] | 871 | |
---|
[751] | 872 | |
---|
[747] | 873 | // Horizontal inter-clusters RAM network DSPIN |
---|
| 874 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = |
---|
[806] | 875 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_inc", X_SIZE-1, Y_SIZE); |
---|
[747] | 876 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = |
---|
[806] | 877 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_dec", X_SIZE-1, Y_SIZE); |
---|
[747] | 878 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = |
---|
[806] | 879 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_inc", X_SIZE-1, Y_SIZE); |
---|
[747] | 880 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = |
---|
[806] | 881 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_dec", X_SIZE-1, Y_SIZE); |
---|
[747] | 882 | |
---|
| 883 | // Vertical inter-clusters RAM network DSPIN |
---|
| 884 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = |
---|
[806] | 885 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_inc", X_SIZE, Y_SIZE-1); |
---|
[747] | 886 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = |
---|
[806] | 887 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_dec", X_SIZE, Y_SIZE-1); |
---|
[747] | 888 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = |
---|
[806] | 889 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_inc", X_SIZE, Y_SIZE-1); |
---|
[747] | 890 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = |
---|
[806] | 891 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_dec", X_SIZE, Y_SIZE-1); |
---|
[747] | 892 | |
---|
| 893 | // Mesh boundaries RAM network DSPIN |
---|
[751] | 894 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = |
---|
[806] | 895 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_in", X_SIZE, Y_SIZE, 4); |
---|
[751] | 896 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = |
---|
[806] | 897 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_out", X_SIZE, Y_SIZE, 4); |
---|
[751] | 898 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = |
---|
[806] | 899 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_in", X_SIZE, Y_SIZE, 4); |
---|
[751] | 900 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = |
---|
[806] | 901 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_out", X_SIZE, Y_SIZE, 4); |
---|
[747] | 902 | |
---|
| 903 | //////////////////////////// |
---|
| 904 | // Loader |
---|
| 905 | //////////////////////////// |
---|
| 906 | |
---|
| 907 | #if USE_ALMOS |
---|
| 908 | soclib::common::Loader loader(almos_bootloader_pathname, |
---|
| 909 | almos_archinfo_pathname, |
---|
| 910 | almos_kernel_pathname); |
---|
| 911 | #else |
---|
| 912 | soclib::common::Loader loader(soft_name); |
---|
| 913 | #endif |
---|
| 914 | |
---|
[756] | 915 | // initialize memory with a value different than 0 (expose software errors |
---|
| 916 | // dues to uninitialized data) |
---|
| 917 | loader.memory_default(0xA0); |
---|
| 918 | |
---|
[747] | 919 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 920 | proc_iss::set_loader(loader); |
---|
| 921 | |
---|
| 922 | //////////////////////////////////////// |
---|
| 923 | // Instanciated Hardware Components |
---|
| 924 | //////////////////////////////////////// |
---|
| 925 | |
---|
| 926 | std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; |
---|
| 927 | |
---|
| 928 | const size_t nb_iox_initiators = (cluster_iob0 != cluster_iob1) ? 5 : 4; |
---|
[769] | 929 | const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 9 : 8; |
---|
[747] | 930 | |
---|
| 931 | // IOX network |
---|
| 932 | VciIoxNetwork<vci_param_ext>* iox_network; |
---|
| 933 | iox_network = new VciIoxNetwork<vci_param_ext>( "iox_network", |
---|
| 934 | maptab_iox, |
---|
| 935 | nb_iox_targets, |
---|
| 936 | nb_iox_initiators ); |
---|
[748] | 937 | |
---|
[747] | 938 | // Network Controller |
---|
| 939 | VciMultiNic<vci_param_ext>* mnic; |
---|
| 940 | mnic = new VciMultiNic<vci_param_ext>( "mnic", |
---|
| 941 | IntTab(0, IOX_MNIC_TGT_ID), |
---|
| 942 | maptab_iox, |
---|
| 943 | NB_NIC_CHANNELS, |
---|
| 944 | 0, // mac_4 address |
---|
| 945 | 0, // mac_2 address |
---|
| 946 | nic_rx_name, |
---|
| 947 | nic_tx_name); |
---|
| 948 | |
---|
| 949 | // Frame Buffer |
---|
| 950 | VciFrameBuffer<vci_param_ext>* fbuf; |
---|
| 951 | fbuf = new VciFrameBuffer<vci_param_ext>( "fbuf", |
---|
| 952 | IntTab(0, IOX_FBUF_TGT_ID), |
---|
| 953 | maptab_iox, |
---|
| 954 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
---|
| 955 | |
---|
| 956 | // Block Device |
---|
| 957 | // for AHCI |
---|
| 958 | // std::vector<std::string> filenames; |
---|
| 959 | // filenames.push_back(disk_name); // one single disk |
---|
| 960 | VciBlockDeviceTsar<vci_param_ext>* bdev; |
---|
| 961 | bdev = new VciBlockDeviceTsar<vci_param_ext>( "bdev", |
---|
| 962 | maptab_iox, |
---|
| 963 | IntTab(0, BDEV_LOCAL_SRCID), |
---|
| 964 | IntTab(0, IOX_BDEV_TGT_ID), |
---|
| 965 | disk_name, |
---|
| 966 | 512, // block size |
---|
| 967 | 64, // burst size (bytes) |
---|
| 968 | 0 ); // disk latency |
---|
| 969 | |
---|
| 970 | // Chained Buffer DMA controller |
---|
| 971 | VciChbufDma<vci_param_ext>* cdma; |
---|
| 972 | cdma = new VciChbufDma<vci_param_ext>( "cdma", |
---|
| 973 | maptab_iox, |
---|
| 974 | IntTab(0, CDMA_LOCAL_SRCID), |
---|
| 975 | IntTab(0, IOX_CDMA_TGT_ID), |
---|
| 976 | 64, // burst size (bytes) |
---|
| 977 | 2*NB_NIC_CHANNELS ); |
---|
| 978 | // Multi-TTY controller |
---|
| 979 | std::vector<std::string> vect_names; |
---|
| 980 | for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ ) |
---|
| 981 | { |
---|
| 982 | std::ostringstream term_name; |
---|
| 983 | term_name << "term" << tid; |
---|
| 984 | vect_names.push_back(term_name.str().c_str()); |
---|
| 985 | } |
---|
| 986 | VciMultiTty<vci_param_ext>* mtty; |
---|
| 987 | mtty = new VciMultiTty<vci_param_ext>( "mtty", |
---|
| 988 | IntTab(0, IOX_MTTY_TGT_ID), |
---|
| 989 | maptab_iox, |
---|
| 990 | vect_names); |
---|
| 991 | |
---|
| 992 | // IOPIC |
---|
| 993 | VciIopic<vci_param_ext>* iopi; |
---|
| 994 | iopi = new VciIopic<vci_param_ext>( "iopi", |
---|
| 995 | maptab_iox, |
---|
| 996 | IntTab(0, IOPI_LOCAL_SRCID), |
---|
| 997 | IntTab(0, IOX_IOPI_TGT_ID), |
---|
| 998 | 32 ); // number of input HWI |
---|
[748] | 999 | |
---|
[769] | 1000 | // Simhelper |
---|
| 1001 | VciSimhelper<vci_param_ext>* simh; |
---|
| 1002 | simh = new VciSimhelper<vci_param_ext>("simh", |
---|
| 1003 | IntTab(0, IOX_SIMH_TGT_ID), |
---|
| 1004 | maptab_iox ); |
---|
| 1005 | |
---|
[747] | 1006 | // Clusters |
---|
| 1007 | TsarIobCluster<vci_param_int, |
---|
| 1008 | vci_param_ext, |
---|
| 1009 | dspin_int_cmd_width, |
---|
| 1010 | dspin_int_rsp_width, |
---|
| 1011 | dspin_ram_cmd_width, |
---|
[806] | 1012 | dspin_ram_rsp_width>* clusters[X_SIZE][Y_SIZE]; |
---|
[747] | 1013 | |
---|
| 1014 | #if USE_OPENMP |
---|
| 1015 | #pragma omp parallel |
---|
| 1016 | { |
---|
| 1017 | #pragma omp for |
---|
| 1018 | #endif |
---|
[806] | 1019 | for(size_t i = 0; i < (X_SIZE * Y_SIZE); i++) |
---|
[747] | 1020 | { |
---|
[806] | 1021 | size_t x = i / Y_SIZE; |
---|
| 1022 | size_t y = i % Y_SIZE; |
---|
[747] | 1023 | |
---|
| 1024 | #if USE_OPENMP |
---|
| 1025 | #pragma omp critical |
---|
| 1026 | { |
---|
| 1027 | #endif |
---|
| 1028 | std::cout << std::endl; |
---|
| 1029 | std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; |
---|
| 1030 | std::cout << std::endl; |
---|
| 1031 | |
---|
[855] | 1032 | const bool is_iob0 = (cluster(x, y) == cluster_iob0); |
---|
| 1033 | const bool is_iob1 = (cluster(x, y) == cluster_iob1); |
---|
[747] | 1034 | const bool is_io_cluster = is_iob0 || is_iob1; |
---|
| 1035 | |
---|
| 1036 | const int iox_iob_ini_id = is_iob0 ? |
---|
| 1037 | IOX_IOB0_INI_ID : |
---|
| 1038 | IOX_IOB1_INI_ID ; |
---|
| 1039 | const int iox_iob_tgt_id = is_iob0 ? |
---|
| 1040 | IOX_IOB0_TGT_ID : |
---|
| 1041 | IOX_IOB1_TGT_ID ; |
---|
| 1042 | |
---|
| 1043 | std::ostringstream sc; |
---|
| 1044 | sc << "cluster_" << x << "_" << y; |
---|
| 1045 | clusters[x][y] = new TsarIobCluster<vci_param_int, |
---|
| 1046 | vci_param_ext, |
---|
| 1047 | dspin_int_cmd_width, |
---|
| 1048 | dspin_int_rsp_width, |
---|
| 1049 | dspin_ram_cmd_width, |
---|
| 1050 | dspin_ram_rsp_width> |
---|
| 1051 | ( |
---|
| 1052 | sc.str().c_str(), |
---|
| 1053 | NB_PROCS_MAX, |
---|
| 1054 | NB_DMA_CHANNELS, |
---|
| 1055 | x, |
---|
| 1056 | y, |
---|
[806] | 1057 | X_SIZE, |
---|
| 1058 | Y_SIZE, |
---|
[747] | 1059 | |
---|
[806] | 1060 | P_WIDTH, |
---|
| 1061 | |
---|
[747] | 1062 | maptab_int, |
---|
| 1063 | maptab_ram, |
---|
| 1064 | maptab_iox, |
---|
| 1065 | |
---|
[806] | 1066 | X_WIDTH, |
---|
| 1067 | Y_WIDTH, |
---|
| 1068 | vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width, |
---|
[747] | 1069 | |
---|
| 1070 | INT_MEMC_TGT_ID, |
---|
| 1071 | INT_XICU_TGT_ID, |
---|
| 1072 | INT_MDMA_TGT_ID, |
---|
[748] | 1073 | INT_BROM_TGT_ID, |
---|
[747] | 1074 | INT_IOBX_TGT_ID, |
---|
| 1075 | |
---|
| 1076 | INT_PROC_INI_ID, |
---|
| 1077 | INT_MDMA_INI_ID, |
---|
| 1078 | INT_IOBX_INI_ID, |
---|
| 1079 | |
---|
| 1080 | RAM_XRAM_TGT_ID, |
---|
| 1081 | |
---|
| 1082 | RAM_MEMC_INI_ID, |
---|
| 1083 | RAM_IOBX_INI_ID, |
---|
| 1084 | |
---|
| 1085 | is_io_cluster, |
---|
| 1086 | iox_iob_tgt_id, |
---|
| 1087 | iox_iob_ini_id, |
---|
| 1088 | |
---|
| 1089 | MEMC_WAYS, |
---|
| 1090 | MEMC_SETS, |
---|
| 1091 | L1_IWAYS, |
---|
| 1092 | L1_ISETS, |
---|
| 1093 | L1_DWAYS, |
---|
| 1094 | L1_DSETS, |
---|
| 1095 | XRAM_LATENCY, |
---|
| 1096 | XCU_NB_INPUTS, |
---|
| 1097 | |
---|
[748] | 1098 | distributed_boot, |
---|
| 1099 | |
---|
[747] | 1100 | loader, |
---|
| 1101 | |
---|
| 1102 | frozen_cycles, |
---|
| 1103 | debug_from, |
---|
[855] | 1104 | debug_ok and (cluster(x, y) == debug_memc_id), |
---|
| 1105 | debug_ok and (cluster(x, y) == (debug_proc_id >> P_WIDTH)), |
---|
[747] | 1106 | debug_ok and debug_iob |
---|
| 1107 | ); |
---|
| 1108 | |
---|
| 1109 | #if USE_OPENMP |
---|
| 1110 | } // end critical |
---|
| 1111 | #endif |
---|
| 1112 | } // end for |
---|
| 1113 | #if USE_OPENMP |
---|
| 1114 | } |
---|
| 1115 | #endif |
---|
| 1116 | |
---|
[855] | 1117 | // disable all interfaces of the faulty router |
---|
| 1118 | if (faulty_router_id != 0xFFFFFFFF) |
---|
| 1119 | { |
---|
| 1120 | int faulty_x = faulty_router_id >> Y_WIDTH; |
---|
| 1121 | int faulty_y = faulty_router_id & ((1 << Y_WIDTH) - 1); |
---|
| 1122 | clusters[faulty_x][faulty_y]->int_router_cmd[0]->set_disable_mask(0x1F); |
---|
| 1123 | } |
---|
| 1124 | |
---|
[747] | 1125 | std::cout << std::endl; |
---|
| 1126 | |
---|
| 1127 | /////////////////////////////////////////////////////////////////////////////// |
---|
| 1128 | // Net-list |
---|
| 1129 | /////////////////////////////////////////////////////////////////////////////// |
---|
| 1130 | |
---|
| 1131 | // IOX network connexion |
---|
| 1132 | iox_network->p_clk (signal_clk); |
---|
| 1133 | iox_network->p_resetn (signal_resetn); |
---|
| 1134 | iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); |
---|
| 1135 | iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev); |
---|
| 1136 | iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); |
---|
| 1137 | iox_network->p_to_ini[IOX_IOPI_INI_ID] (signal_vci_ini_iopi); |
---|
| 1138 | |
---|
| 1139 | iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); |
---|
| 1140 | iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); |
---|
| 1141 | iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); |
---|
| 1142 | iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); |
---|
| 1143 | iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); |
---|
| 1144 | iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); |
---|
| 1145 | iox_network->p_to_tgt[IOX_IOPI_TGT_ID] (signal_vci_tgt_iopi); |
---|
[769] | 1146 | iox_network->p_to_tgt[IOX_SIMH_TGT_ID] (signal_vci_tgt_simh); |
---|
[747] | 1147 | |
---|
| 1148 | if (cluster_iob0 != cluster_iob1) |
---|
| 1149 | { |
---|
| 1150 | iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); |
---|
| 1151 | iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); |
---|
| 1152 | } |
---|
| 1153 | |
---|
| 1154 | // BDEV connexion |
---|
| 1155 | bdev->p_clk (signal_clk); |
---|
| 1156 | bdev->p_resetn (signal_resetn); |
---|
| 1157 | bdev->p_irq (signal_irq_bdev); |
---|
| 1158 | bdev->p_vci_target (signal_vci_tgt_bdev); |
---|
| 1159 | bdev->p_vci_initiator (signal_vci_ini_bdev); |
---|
| 1160 | |
---|
| 1161 | std::cout << " - BDEV connected" << std::endl; |
---|
| 1162 | |
---|
| 1163 | // FBUF connexion |
---|
| 1164 | fbuf->p_clk (signal_clk); |
---|
| 1165 | fbuf->p_resetn (signal_resetn); |
---|
| 1166 | fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
| 1167 | |
---|
| 1168 | std::cout << " - FBUF connected" << std::endl; |
---|
| 1169 | |
---|
| 1170 | // MNIC connexion |
---|
| 1171 | mnic->p_clk (signal_clk); |
---|
| 1172 | mnic->p_resetn (signal_resetn); |
---|
| 1173 | mnic->p_vci (signal_vci_tgt_mnic); |
---|
| 1174 | for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) |
---|
| 1175 | { |
---|
| 1176 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
| 1177 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
| 1178 | } |
---|
| 1179 | |
---|
| 1180 | std::cout << " - MNIC connected" << std::endl; |
---|
| 1181 | |
---|
| 1182 | // MTTY connexion |
---|
| 1183 | mtty->p_clk (signal_clk); |
---|
| 1184 | mtty->p_resetn (signal_resetn); |
---|
| 1185 | mtty->p_vci (signal_vci_tgt_mtty); |
---|
| 1186 | mtty->p_irq[0] (signal_irq_mtty_rx); |
---|
| 1187 | |
---|
| 1188 | std::cout << " - MTTY connected" << std::endl; |
---|
| 1189 | |
---|
| 1190 | // CDMA connexion |
---|
| 1191 | cdma->p_clk (signal_clk); |
---|
| 1192 | cdma->p_resetn (signal_resetn); |
---|
| 1193 | cdma->p_vci_target (signal_vci_tgt_cdma); |
---|
| 1194 | cdma->p_vci_initiator (signal_vci_ini_cdma); |
---|
| 1195 | for ( size_t i=0 ; i<(NB_NIC_CHANNELS*2) ; i++) |
---|
| 1196 | { |
---|
| 1197 | cdma->p_irq[i] (signal_irq_cdma[i]); |
---|
| 1198 | } |
---|
| 1199 | |
---|
| 1200 | std::cout << " - CDMA connected" << std::endl; |
---|
| 1201 | |
---|
| 1202 | // IOPI connexion |
---|
| 1203 | iopi->p_clk (signal_clk); |
---|
| 1204 | iopi->p_resetn (signal_resetn); |
---|
| 1205 | iopi->p_vci_target (signal_vci_tgt_iopi); |
---|
| 1206 | iopi->p_vci_initiator (signal_vci_ini_iopi); |
---|
| 1207 | for ( size_t i=0 ; i<32 ; i++) |
---|
| 1208 | { |
---|
| 1209 | if (i < NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_rx[i]); |
---|
| 1210 | else if(i < 2 ) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1211 | else if(i < 2+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-2]); |
---|
| 1212 | else if(i < 4 ) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1213 | else if(i < 4+NB_CMA_CHANNELS) iopi->p_hwi[i] (signal_irq_cdma[i-4]); |
---|
| 1214 | else if(i < 8) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1215 | else if(i == 8) iopi->p_hwi[i] (signal_irq_bdev); |
---|
| 1216 | else if(i == 9) iopi->p_hwi[i] (signal_irq_mtty_rx); |
---|
| 1217 | else iopi->p_hwi[i] (signal_irq_false); |
---|
| 1218 | } |
---|
| 1219 | |
---|
| 1220 | std::cout << " - IOPIC connected" << std::endl; |
---|
| 1221 | |
---|
[769] | 1222 | // Simhelper connexion |
---|
| 1223 | simh->p_clk(signal_clk); |
---|
| 1224 | simh->p_resetn(signal_resetn); |
---|
| 1225 | simh->p_vci(signal_vci_tgt_simh); |
---|
[747] | 1226 | |
---|
| 1227 | // IOB0 cluster connexion to IOX network |
---|
| 1228 | (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); |
---|
| 1229 | (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); |
---|
| 1230 | |
---|
| 1231 | // IOB1 cluster connexion to IOX network |
---|
| 1232 | // (only when there is more than 1 cluster) |
---|
| 1233 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 1234 | { |
---|
[806] | 1235 | (*clusters[X_SIZE-1][Y_SIZE-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); |
---|
| 1236 | (*clusters[X_SIZE-1][Y_SIZE-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); |
---|
[747] | 1237 | } |
---|
| 1238 | |
---|
| 1239 | // All clusters Clock & RESET connexions |
---|
[806] | 1240 | for ( size_t x = 0; x < (X_SIZE); x++ ) |
---|
[747] | 1241 | { |
---|
[806] | 1242 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
[747] | 1243 | { |
---|
| 1244 | clusters[x][y]->p_clk (signal_clk); |
---|
| 1245 | clusters[x][y]->p_resetn (signal_resetn); |
---|
| 1246 | } |
---|
| 1247 | } |
---|
| 1248 | |
---|
| 1249 | // Inter Clusters horizontal connections |
---|
[806] | 1250 | if (X_SIZE > 1) |
---|
[747] | 1251 | { |
---|
[806] | 1252 | for (size_t x = 0; x < (X_SIZE-1); x++) |
---|
[747] | 1253 | { |
---|
[806] | 1254 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
[747] | 1255 | { |
---|
| 1256 | for (size_t k = 0; k < 3; k++) |
---|
| 1257 | { |
---|
| 1258 | clusters[x][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1259 | clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1260 | clusters[x][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
| 1261 | clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
| 1262 | } |
---|
| 1263 | |
---|
| 1264 | for (size_t k = 0; k < 2; k++) |
---|
| 1265 | { |
---|
| 1266 | clusters[x][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1267 | clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1268 | clusters[x][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
| 1269 | clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
| 1270 | } |
---|
| 1271 | |
---|
| 1272 | clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1273 | clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1274 | clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1275 | clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1276 | clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1277 | clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1278 | clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1279 | clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1280 | } |
---|
| 1281 | } |
---|
| 1282 | } |
---|
| 1283 | |
---|
| 1284 | std::cout << std::endl << "Horizontal connections established" << std::endl; |
---|
| 1285 | |
---|
| 1286 | // Inter Clusters vertical connections |
---|
[806] | 1287 | if (Y_SIZE > 1) |
---|
[747] | 1288 | { |
---|
[806] | 1289 | for (size_t y = 0; y < (Y_SIZE-1); y++) |
---|
[747] | 1290 | { |
---|
[806] | 1291 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 1292 | { |
---|
| 1293 | for (size_t k = 0; k < 3; k++) |
---|
| 1294 | { |
---|
| 1295 | clusters[x][y]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1296 | clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1297 | clusters[x][y]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
| 1298 | clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
| 1299 | } |
---|
| 1300 | |
---|
| 1301 | for (size_t k = 0; k < 2; k++) |
---|
| 1302 | { |
---|
| 1303 | clusters[x][y]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1304 | clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1305 | clusters[x][y]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
| 1306 | clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
| 1307 | } |
---|
| 1308 | |
---|
| 1309 | clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1310 | clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1311 | clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1312 | clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1313 | clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1314 | clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1315 | clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1316 | clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1317 | } |
---|
| 1318 | } |
---|
| 1319 | } |
---|
| 1320 | |
---|
| 1321 | std::cout << "Vertical connections established" << std::endl; |
---|
| 1322 | |
---|
| 1323 | // East & West boundary cluster connections |
---|
[806] | 1324 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
[747] | 1325 | { |
---|
| 1326 | for (size_t k = 0; k < 3; k++) |
---|
| 1327 | { |
---|
[751] | 1328 | clusters[0][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_false_int_cmd_in[0][y][WEST][k]); |
---|
| 1329 | clusters[0][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_false_int_cmd_out[0][y][WEST][k]); |
---|
[806] | 1330 | clusters[X_SIZE-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[X_SIZE-1][y][EAST][k]); |
---|
| 1331 | clusters[X_SIZE-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[X_SIZE-1][y][EAST][k]); |
---|
[747] | 1332 | } |
---|
| 1333 | |
---|
| 1334 | for (size_t k = 0; k < 2; k++) |
---|
| 1335 | { |
---|
[751] | 1336 | clusters[0][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_false_int_rsp_in[0][y][WEST][k]); |
---|
| 1337 | clusters[0][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_false_int_rsp_out[0][y][WEST][k]); |
---|
[806] | 1338 | clusters[X_SIZE-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[X_SIZE-1][y][EAST][k]); |
---|
| 1339 | clusters[X_SIZE-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[X_SIZE-1][y][EAST][k]); |
---|
[747] | 1340 | } |
---|
| 1341 | |
---|
[751] | 1342 | clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); |
---|
| 1343 | clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); |
---|
| 1344 | clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); |
---|
| 1345 | clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); |
---|
[747] | 1346 | |
---|
[806] | 1347 | clusters[X_SIZE-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[X_SIZE-1][y][EAST]); |
---|
| 1348 | clusters[X_SIZE-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[X_SIZE-1][y][EAST]); |
---|
| 1349 | clusters[X_SIZE-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[X_SIZE-1][y][EAST]); |
---|
| 1350 | clusters[X_SIZE-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[X_SIZE-1][y][EAST]); |
---|
[747] | 1351 | } |
---|
| 1352 | |
---|
| 1353 | std::cout << "East & West boundaries established" << std::endl; |
---|
| 1354 | |
---|
| 1355 | // North & South boundary clusters connections |
---|
[806] | 1356 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 1357 | { |
---|
| 1358 | for (size_t k = 0; k < 3; k++) |
---|
| 1359 | { |
---|
[751] | 1360 | clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); |
---|
| 1361 | clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); |
---|
[806] | 1362 | clusters[x][Y_SIZE-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][Y_SIZE-1][NORTH][k]); |
---|
| 1363 | clusters[x][Y_SIZE-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][Y_SIZE-1][NORTH][k]); |
---|
[747] | 1364 | } |
---|
| 1365 | |
---|
| 1366 | for (size_t k = 0; k < 2; k++) |
---|
| 1367 | { |
---|
[751] | 1368 | clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); |
---|
| 1369 | clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); |
---|
[806] | 1370 | clusters[x][Y_SIZE-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][Y_SIZE-1][NORTH][k]); |
---|
| 1371 | clusters[x][Y_SIZE-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][Y_SIZE-1][NORTH][k]); |
---|
[747] | 1372 | } |
---|
| 1373 | |
---|
[751] | 1374 | clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); |
---|
| 1375 | clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); |
---|
| 1376 | clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); |
---|
| 1377 | clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); |
---|
[747] | 1378 | |
---|
[806] | 1379 | clusters[x][Y_SIZE-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][Y_SIZE-1][NORTH]); |
---|
| 1380 | clusters[x][Y_SIZE-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][Y_SIZE-1][NORTH]); |
---|
| 1381 | clusters[x][Y_SIZE-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][Y_SIZE-1][NORTH]); |
---|
| 1382 | clusters[x][Y_SIZE-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][Y_SIZE-1][NORTH]); |
---|
[747] | 1383 | } |
---|
| 1384 | |
---|
| 1385 | std::cout << "North & South boundaries established" << std::endl << std::endl; |
---|
| 1386 | |
---|
| 1387 | //////////////////////////////////////////////////////// |
---|
| 1388 | // Simulation |
---|
| 1389 | /////////////////////////////////////////////////////// |
---|
| 1390 | |
---|
| 1391 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
| 1392 | |
---|
| 1393 | signal_resetn = false; |
---|
| 1394 | signal_irq_false = false; |
---|
| 1395 | |
---|
[751] | 1396 | // network boundaries signals |
---|
[806] | 1397 | for (size_t x = 0; x < X_SIZE ; x++) |
---|
[751] | 1398 | { |
---|
[806] | 1399 | for (size_t y = 0; y < Y_SIZE ; y++) |
---|
[751] | 1400 | { |
---|
| 1401 | for (size_t a = 0; a < 4; a++) |
---|
| 1402 | { |
---|
| 1403 | for (size_t k = 0; k < 3; k++) |
---|
| 1404 | { |
---|
| 1405 | signal_dspin_false_int_cmd_in[x][y][a][k].write = false; |
---|
| 1406 | signal_dspin_false_int_cmd_in[x][y][a][k].read = true; |
---|
| 1407 | signal_dspin_false_int_cmd_out[x][y][a][k].write = false; |
---|
| 1408 | signal_dspin_false_int_cmd_out[x][y][a][k].read = true; |
---|
| 1409 | } |
---|
[750] | 1410 | |
---|
[751] | 1411 | for (size_t k = 0; k < 2; k++) |
---|
| 1412 | { |
---|
| 1413 | signal_dspin_false_int_rsp_in[x][y][a][k].write = false; |
---|
| 1414 | signal_dspin_false_int_rsp_in[x][y][a][k].read = true; |
---|
| 1415 | signal_dspin_false_int_rsp_out[x][y][a][k].write = false; |
---|
| 1416 | signal_dspin_false_int_rsp_out[x][y][a][k].read = true; |
---|
| 1417 | } |
---|
| 1418 | |
---|
| 1419 | signal_dspin_false_ram_cmd_in[x][y][a].write = false; |
---|
| 1420 | signal_dspin_false_ram_cmd_in[x][y][a].read = true; |
---|
| 1421 | signal_dspin_false_ram_cmd_out[x][y][a].write = false; |
---|
| 1422 | signal_dspin_false_ram_cmd_out[x][y][a].read = true; |
---|
| 1423 | |
---|
| 1424 | signal_dspin_false_ram_rsp_in[x][y][a].write = false; |
---|
| 1425 | signal_dspin_false_ram_rsp_in[x][y][a].read = true; |
---|
| 1426 | signal_dspin_false_ram_rsp_out[x][y][a].write = false; |
---|
| 1427 | signal_dspin_false_ram_rsp_out[x][y][a].read = true; |
---|
| 1428 | } |
---|
| 1429 | } |
---|
| 1430 | } |
---|
| 1431 | |
---|
[750] | 1432 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 1433 | signal_resetn = true; |
---|
| 1434 | |
---|
| 1435 | // simulation loop |
---|
[855] | 1436 | struct timeval t1, t2; |
---|
[750] | 1437 | |
---|
[766] | 1438 | // cycles between stats |
---|
| 1439 | const size_t stats_period = 100000; |
---|
| 1440 | const size_t simul_period = debug_ok ? debug_period : stats_period; |
---|
[747] | 1441 | |
---|
[766] | 1442 | for (size_t n = 0; n < ncycles; n += simul_period) |
---|
[750] | 1443 | { |
---|
| 1444 | // stats display |
---|
[766] | 1445 | if((n % stats_period) == 0) |
---|
[750] | 1446 | { |
---|
[766] | 1447 | if (n > 0) |
---|
| 1448 | { |
---|
| 1449 | gettimeofday(&t2, NULL); |
---|
[747] | 1450 | |
---|
[766] | 1451 | uint64_t ms1 = (uint64_t) t1.tv_sec * 1000ULL + |
---|
| 1452 | (uint64_t) t1.tv_usec / 1000; |
---|
| 1453 | uint64_t ms2 = (uint64_t) t2.tv_sec * 1000ULL + |
---|
| 1454 | (uint64_t) t2.tv_usec / 1000; |
---|
| 1455 | std::cerr << "### cycle = " << n << " / frequency (Khz) = " |
---|
| 1456 | << (double) stats_period / (double) (ms2 - ms1) << std::endl; |
---|
| 1457 | } |
---|
[747] | 1458 | |
---|
[750] | 1459 | gettimeofday(&t1, NULL); |
---|
| 1460 | } |
---|
[747] | 1461 | |
---|
[750] | 1462 | // Monitor a specific address for one L1 cache |
---|
| 1463 | // clusters[1][1]->proc[0]->cache_monitor(0x50090ULL); |
---|
[747] | 1464 | |
---|
[750] | 1465 | // Monitor a specific address for one L2 cache |
---|
| 1466 | // clusters[0][0]->memc->cache_monitor( 0x170000ULL); |
---|
[747] | 1467 | |
---|
[750] | 1468 | // Monitor a specific address for one XRAM |
---|
| 1469 | // if (n == 3000000) clusters[0][0]->xram->start_monitor( 0x170000ULL , 64); |
---|
[747] | 1470 | |
---|
[750] | 1471 | if (debug_ok and (n > debug_from) and (n % debug_period == 0)) |
---|
| 1472 | { |
---|
| 1473 | std::cout << "****************** cycle " << std::dec << n ; |
---|
| 1474 | std::cout << " ************************************************" << std::endl; |
---|
[747] | 1475 | |
---|
[750] | 1476 | // trace proc[debug_proc_id] |
---|
| 1477 | if ( debug_proc_id != 0xFFFFFFFF ) |
---|
| 1478 | { |
---|
[855] | 1479 | size_t l = debug_proc_id & ((1 << P_WIDTH) - 1); |
---|
| 1480 | size_t cluster_xy = debug_proc_id >> P_WIDTH ; |
---|
| 1481 | size_t x = cluster_xy >> Y_WIDTH; |
---|
| 1482 | size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); |
---|
[747] | 1483 | |
---|
[750] | 1484 | clusters[x][y]->proc[l]->print_trace(1); |
---|
| 1485 | std::ostringstream proc_signame; |
---|
| 1486 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
| 1487 | clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); |
---|
[747] | 1488 | |
---|
[750] | 1489 | clusters[x][y]->xicu->print_trace(l); |
---|
| 1490 | std::ostringstream xicu_signame; |
---|
| 1491 | xicu_signame << "[SIG]XICU_" << x << "_" << y; |
---|
| 1492 | clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); |
---|
[747] | 1493 | |
---|
[750] | 1494 | // clusters[x][y]->mdma->print_trace(); |
---|
| 1495 | // std::ostringstream mdma_signame; |
---|
| 1496 | // mdma_signame << "[SIG]MDMA_" << x << "_" << y; |
---|
| 1497 | // clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_signame.str()); |
---|
[748] | 1498 | |
---|
[750] | 1499 | if( clusters[x][y]->signal_proc_it[l].read() ) |
---|
| 1500 | std::cout << "### IRQ_PROC_" << std::dec |
---|
| 1501 | << x << "_" << y << "_" << l << " ACTIVE" << std::endl; |
---|
| 1502 | } |
---|
[747] | 1503 | |
---|
[750] | 1504 | // trace memc[debug_memc_id] |
---|
| 1505 | if ( debug_memc_id != 0xFFFFFFFF ) |
---|
| 1506 | { |
---|
[855] | 1507 | size_t x = debug_memc_id >> Y_WIDTH; |
---|
| 1508 | size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); |
---|
[747] | 1509 | |
---|
[750] | 1510 | clusters[x][y]->memc->print_trace(0); |
---|
| 1511 | std::ostringstream smemc_tgt; |
---|
| 1512 | smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; |
---|
| 1513 | clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); |
---|
| 1514 | std::ostringstream smemc_ini; |
---|
| 1515 | smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; |
---|
| 1516 | clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); |
---|
[747] | 1517 | |
---|
[750] | 1518 | clusters[x][y]->xram->print_trace(); |
---|
| 1519 | std::ostringstream sxram_tgt; |
---|
| 1520 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
| 1521 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
| 1522 | } |
---|
[747] | 1523 | |
---|
| 1524 | |
---|
[750] | 1525 | // trace XRAM and XRAM network routers in cluster[debug_xram_id] |
---|
| 1526 | if ( debug_xram_id != 0xFFFFFFFF ) |
---|
| 1527 | { |
---|
[855] | 1528 | size_t x = debug_xram_id >> Y_WIDTH; |
---|
| 1529 | size_t y = debug_xram_id & ((1 << Y_WIDTH) - 1); |
---|
[747] | 1530 | |
---|
[750] | 1531 | clusters[x][y]->xram->print_trace(); |
---|
| 1532 | std::ostringstream sxram_tgt; |
---|
| 1533 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
| 1534 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
[747] | 1535 | |
---|
[750] | 1536 | clusters[x][y]->ram_router_cmd->print_trace(); |
---|
| 1537 | clusters[x][y]->ram_router_rsp->print_trace(); |
---|
| 1538 | } |
---|
[747] | 1539 | |
---|
[750] | 1540 | // trace iob, iox and external peripherals |
---|
| 1541 | if ( debug_iob ) |
---|
| 1542 | { |
---|
| 1543 | clusters[0][0]->iob->print_trace(); |
---|
[806] | 1544 | clusters[X_SIZE-1][Y_SIZE-1]->iob->print_trace(); |
---|
[750] | 1545 | // clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); |
---|
| 1546 | // clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); |
---|
| 1547 | // clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); |
---|
[747] | 1548 | |
---|
[750] | 1549 | signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); |
---|
| 1550 | signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); |
---|
[747] | 1551 | |
---|
[750] | 1552 | // cdma->print_trace(); |
---|
| 1553 | // signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT"); |
---|
| 1554 | // signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI"); |
---|
[747] | 1555 | |
---|
[750] | 1556 | // mtty->print_trace(); |
---|
| 1557 | // signal_vci_tgt_mtty.print_trace("[SIG]IOX_MTTY_TGT"); |
---|
[747] | 1558 | |
---|
[750] | 1559 | bdev->print_trace(); |
---|
| 1560 | signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); |
---|
| 1561 | signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); |
---|
[747] | 1562 | |
---|
[750] | 1563 | mnic->print_trace(); |
---|
| 1564 | signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); |
---|
[747] | 1565 | |
---|
[750] | 1566 | // fbuf->print_trace(); |
---|
| 1567 | // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF"); |
---|
[747] | 1568 | |
---|
[750] | 1569 | iopi->print_trace(); |
---|
| 1570 | signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); |
---|
| 1571 | signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); |
---|
[769] | 1572 | |
---|
| 1573 | signal_vci_tgt_simh.print_trace("[SIG]SIMH_TGT"); |
---|
| 1574 | |
---|
[750] | 1575 | iox_network->print_trace(); |
---|
[747] | 1576 | |
---|
[750] | 1577 | // interrupts |
---|
| 1578 | if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVE" << std::endl; |
---|
| 1579 | if (signal_irq_mtty_rx) std::cout << "### IRQ_MTTY ACTIVE" << std::endl; |
---|
| 1580 | if (signal_irq_mnic_rx[0]) std::cout << "### IRQ_MNIC_RX[0] ACTIVE" << std::endl; |
---|
| 1581 | if (signal_irq_mnic_rx[1]) std::cout << "### IRQ_MNIC_RX[1] ACTIVE" << std::endl; |
---|
| 1582 | if (signal_irq_mnic_tx[0]) std::cout << "### IRQ_MNIC_TX[0] ACTIVE" << std::endl; |
---|
| 1583 | if (signal_irq_mnic_tx[1]) std::cout << "### IRQ_MNIC_TX[1] ACTIVE" << std::endl; |
---|
| 1584 | } |
---|
| 1585 | } |
---|
[747] | 1586 | |
---|
[766] | 1587 | sc_start(sc_core::sc_time(simul_period, SC_NS)); |
---|
[750] | 1588 | } |
---|
| 1589 | return EXIT_SUCCESS; |
---|
[747] | 1590 | } |
---|
| 1591 | |
---|
| 1592 | int sc_main (int argc, char *argv[]) |
---|
| 1593 | { |
---|
| 1594 | try { |
---|
| 1595 | return _main(argc, argv); |
---|
[769] | 1596 | } catch (soclib::exception::RunTimeError &e) { |
---|
| 1597 | std::cout << "RunTimeError: " << e.what() << std::endl; |
---|
[747] | 1598 | } catch (std::exception &e) { |
---|
| 1599 | std::cout << e.what() << std::endl; |
---|
| 1600 | } catch (...) { |
---|
| 1601 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 1602 | throw; |
---|
| 1603 | } |
---|
| 1604 | return 1; |
---|
| 1605 | } |
---|
| 1606 | |
---|
| 1607 | |
---|
| 1608 | // Local Variables: |
---|
| 1609 | // tab-width: 3 |
---|
| 1610 | // c-basic-offset: 3 |
---|
| 1611 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 1612 | // indent-tabs-mode: nil |
---|
| 1613 | // End: |
---|
| 1614 | |
---|
| 1615 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
| 1616 | |
---|
| 1617 | |
---|
| 1618 | |
---|