[747] | 1 | /////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: top.cpp (for tsar_generic_iob platform) |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : august 2013 |
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| 6 | // This program is released under the GNU public license |
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[875] | 7 | // |
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| 8 | // Modified by: Cesar Fuguet |
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[747] | 9 | /////////////////////////////////////////////////////////////////////////////// |
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| 10 | // This file define a generic TSAR architecture with an IO network emulating |
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| 11 | // an external bus (i.e. Hypertransport) to access 7 external peripherals: |
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| 12 | // |
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| 13 | // - FBUF : Frame Buffer |
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| 14 | // - MTTY : multi TTY (one channel) |
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| 15 | // - MNIC : Network controller (up to 2 channels) |
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| 16 | // - CDMA : Chained Buffer DMA controller (up to 4 channels) |
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| 17 | // - BDEV : Dlock Device controler (one channel) |
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| 18 | // - IOPI : HWI to SWI translator. |
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[875] | 19 | // - SIMH : Simulation Helper |
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[747] | 20 | // |
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| 21 | // The internal physical address space is 40 bits, and the cluster index |
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| 22 | // is defined by the 8 MSB bits, using a fixed format: X is encoded on 4 bits, |
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| 23 | // Y is encodes on 4 bits, whatever the actual mesh size. |
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| 24 | // => at most 16 * 16 clusters. Each cluster contains up to 4 processors. |
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| 25 | // |
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| 26 | // It contains 3 networks: |
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| 27 | // |
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| 28 | // 1) the "INT" network supports Read/Write transactions |
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| 29 | // between processors and L2 caches or peripherals. |
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| 30 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) |
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| 31 | // It supports also coherence transactions between L1 & L2 caches. |
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| 32 | // 3) the "RAM" network emulates the 3D network between L2 caches |
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| 33 | // and L3 caches, and is implemented as a 2D mesh between the L2 caches, |
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| 34 | // the two IO bridges and the physical RAMs disributed in all clusters. |
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| 35 | // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) |
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| 36 | // 4) the IOX network connects the two IO bridge components to the |
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| 37 | // 7 external peripheral controllers. |
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| 38 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) |
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| 39 | // |
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| 40 | // The external peripherals HWI IRQs are translated to WTI IRQs by the |
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| 41 | // external IOPIC component, that must be configured by the OS to route |
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[875] | 42 | // these WTI IRQS to one or several internal XICU components. |
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[747] | 43 | // - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0] |
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| 44 | // - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0] |
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| 45 | // - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]] |
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| 46 | // - IOPIC HWI[8] connected to IRQ_BDEV |
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[875] | 47 | // - IOPIC HWI[31:16] connected to IRQ_TTY_RX[15:0] |
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[747] | 48 | // |
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| 49 | // Besides the external peripherals, each cluster contains one XICU component, |
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| 50 | // and one multi channels DMA component. |
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| 51 | // The XICU component is mainly used to handle WTI IRQs, as only 5 HWI IRQs |
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| 52 | // are connected to XICU in each cluster: |
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| 53 | // - IRQ_IN[0] : MMC |
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| 54 | // - IRQ_IN[1] : DMA channel 0 |
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| 55 | // - IRQ_IN[2] : DMA channel 1 |
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| 56 | // - IRQ_IN[3] : DMA channel 2 |
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| 57 | // - IRQ_IN[4] : DMA channel 3 |
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| 58 | // |
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[855] | 59 | // All clusters are identical, but cluster(0, 0) and cluster(X_SIZE-1, Y_SIZE-1) |
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[747] | 60 | // contain an extra IO bridge component. These IOB0 & IOB1 components are |
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| 61 | // connected to the three networks (INT, RAM, IOX). |
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| 62 | // |
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| 63 | // - It uses two dspin_local_crossbar per cluster to implement the |
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| 64 | // local interconnect correponding to the INT network. |
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| 65 | // - It uses three dspin_local_crossbar per cluster to implement the |
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| 66 | // local interconnect correponding to the coherence INT network. |
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| 67 | // - It uses two virtual_dspin_router per cluster to implement |
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| 68 | // the INT network (routing both the direct and coherence trafic). |
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| 69 | // - It uses two dspin_router per cluster to implement the RAM network. |
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| 70 | // - It uses the vci_cc_vcache_wrapper. |
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| 71 | // - It uses the vci_mem_cache. |
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| 72 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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| 73 | // - It contains one vci_simple ram per cluster to model the L3 cache. |
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| 74 | // |
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| 75 | // The TsarIobCluster component is defined in files |
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| 76 | // tsar_iob_cluster.* (with * = cpp, h, sd) |
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| 77 | // |
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| 78 | // The main hardware parameters must be defined in the hard_config.h file : |
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| 79 | // - X_SIZE : number of clusters in a row |
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| 80 | // - Y_SIZE : number of clusters in a column |
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| 81 | // - NB_PROCS_MAX : number of processors per cluster (power of 2) |
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[875] | 82 | // - NB_TTY_CHANNELS : number of TTY channels in I/O network (up to 16) |
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[747] | 83 | // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 2) |
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| 84 | // - NB_CMA_CHANNELS : number of CMA channels in I/O network (up to 4) |
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| 85 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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| 86 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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| 87 | // - XCU_NB_INPUTS : number of HWIs = number of WTIs = number of PTIs |
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| 88 | // |
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| 89 | // Some secondary hardware parameters must be defined in this top.cpp file: |
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| 90 | // - XRAM_LATENCY : external ram latency |
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| 91 | // - MEMC_WAYS : L2 cache number of ways |
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| 92 | // - MEMC_SETS : L2 cache number of sets |
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| 93 | // - L1_IWAYS |
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| 94 | // - L1_ISETS |
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| 95 | // - L1_DWAYS |
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| 96 | // - L1_DSETS |
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| 97 | // - BDEV_IMAGE_NAME : file pathname for block device |
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| 98 | // - NIC_TIMEOUT : max number of cycles before closing a container |
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| 99 | // |
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| 100 | // General policy for 40 bits physical address decoding: |
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| 101 | // All physical segments base addresses are multiple of 1 Mbytes |
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| 102 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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[806] | 103 | // The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define |
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[747] | 104 | // the cluster index, and the LADR bits define the local index: |
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| 105 | // |X_ID|Y_ID| LADR | OFFSET | |
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| 106 | // | 4 | 4 | 8 | 24 | |
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| 107 | // |
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| 108 | // General policy for 14 bits SRCID decoding: |
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| 109 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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| 110 | // |X_ID|Y_ID| L_ID | |
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| 111 | // | 4 | 4 | 6 | |
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| 112 | ///////////////////////////////////////////////////////////////////////// |
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| 113 | |
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| 114 | #include <systemc> |
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| 115 | #include <sys/time.h> |
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| 116 | #include <iostream> |
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| 117 | #include <sstream> |
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| 118 | #include <cstdlib> |
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| 119 | #include <cstdarg> |
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[750] | 120 | #include <climits> |
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[747] | 121 | #include <stdint.h> |
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[889] | 122 | #include <vector> |
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[747] | 123 | |
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| 124 | #include "gdbserver.h" |
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| 125 | #include "mapping_table.h" |
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| 126 | |
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| 127 | #include "tsar_iob_cluster.h" |
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| 128 | #include "vci_chbuf_dma.h" |
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| 129 | #include "vci_multi_tty.h" |
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| 130 | #include "vci_multi_nic.h" |
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| 131 | #include "vci_simple_rom.h" |
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| 132 | #include "vci_block_device_tsar.h" |
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| 133 | #include "vci_framebuffer.h" |
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| 134 | #include "vci_iox_network.h" |
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| 135 | #include "vci_iox_network.h" |
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| 136 | #include "vci_iopic.h" |
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[769] | 137 | #include "vci_simhelper.h" |
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[747] | 138 | |
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| 139 | #include "alloc_elems.h" |
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| 140 | |
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| 141 | /////////////////////////////////////////////////// |
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| 142 | // OS |
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| 143 | /////////////////////////////////////////////////// |
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| 144 | #define USE_ALMOS 0 |
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| 145 | |
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| 146 | #define almos_bootloader_pathname "bootloader.bin" |
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| 147 | #define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" |
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| 148 | #define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" |
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| 149 | |
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| 150 | /////////////////////////////////////////////////// |
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| 151 | // Parallelisation |
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| 152 | /////////////////////////////////////////////////// |
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| 153 | #if USE_OPENMP |
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| 154 | #include <omp.h> |
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| 155 | #endif |
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| 156 | |
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| 157 | /////////////////////////////////////////////////////////// |
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| 158 | // DSPIN parameters |
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| 159 | /////////////////////////////////////////////////////////// |
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| 160 | |
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| 161 | #define dspin_int_cmd_width 39 |
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| 162 | #define dspin_int_rsp_width 32 |
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| 163 | |
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| 164 | #define dspin_ram_cmd_width 64 |
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| 165 | #define dspin_ram_rsp_width 64 |
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| 166 | |
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| 167 | /////////////////////////////////////////////////////////// |
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| 168 | // VCI fields width for the 3 VCI networks |
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| 169 | /////////////////////////////////////////////////////////// |
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| 170 | |
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| 171 | #define vci_cell_width_int 4 |
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| 172 | #define vci_cell_width_ext 8 |
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| 173 | |
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| 174 | #define vci_plen_width 8 |
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| 175 | #define vci_address_width 40 |
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| 176 | #define vci_rerror_width 1 |
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| 177 | #define vci_clen_width 1 |
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| 178 | #define vci_rflag_width 1 |
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| 179 | #define vci_srcid_width 14 |
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| 180 | #define vci_pktid_width 4 |
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| 181 | #define vci_trdid_width 4 |
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| 182 | #define vci_wrplen_width 1 |
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| 183 | |
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| 184 | //////////////////////////////////////////////////////////// |
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| 185 | // Main Hardware Parameters values |
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| 186 | //////////////////////i///////////////////////////////////// |
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| 187 | |
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| 188 | #include "hard_config.h" |
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| 189 | |
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| 190 | //////////////////////////////////////////////////////////// |
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| 191 | // Secondary Hardware Parameters values |
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| 192 | //////////////////////i///////////////////////////////////// |
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| 193 | |
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| 194 | #define XRAM_LATENCY 0 |
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| 195 | |
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| 196 | #define MEMC_WAYS 16 |
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| 197 | #define MEMC_SETS 256 |
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| 198 | |
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| 199 | #define L1_IWAYS 4 |
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| 200 | #define L1_ISETS 64 |
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| 201 | |
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| 202 | #define L1_DWAYS 4 |
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| 203 | #define L1_DSETS 64 |
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| 204 | |
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| 205 | #define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" |
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| 206 | |
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| 207 | #define NIC_TIMEOUT 10000 |
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| 208 | |
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| 209 | #define NORTH 0 |
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| 210 | #define SOUTH 1 |
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| 211 | #define EAST 2 |
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| 212 | #define WEST 3 |
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| 213 | |
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[855] | 214 | #define cluster(x, y) ((y) + ((x) << Y_WIDTH)) |
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[747] | 215 | |
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| 216 | //////////////////////////////////////////////////////////// |
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| 217 | // Software to be loaded in ROM & RAM |
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| 218 | //////////////////////i///////////////////////////////////// |
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| 219 | |
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| 220 | #define BOOT_SOFT_NAME "../../softs/tsar_boot/preloader.elf" |
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| 221 | |
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| 222 | //////////////////////////////////////////////////////////// |
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| 223 | // DEBUG Parameters default values |
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| 224 | //////////////////////i///////////////////////////////////// |
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| 225 | |
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[748] | 226 | #define MAX_FROZEN_CYCLES 200000 |
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[747] | 227 | |
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| 228 | ///////////////////////////////////////////////////////// |
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| 229 | // Physical segments definition |
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| 230 | ///////////////////////////////////////////////////////// |
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| 231 | |
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| 232 | // All physical segments base addresses and sizes are defined |
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| 233 | // in the hard_config.h file. For replicated segments, the |
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| 234 | // base address is incremented by a cluster offset: |
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[855] | 235 | // offset = cluster(x, y) << (address_width-X_WIDTH-Y_WIDTH); |
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[747] | 236 | |
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| 237 | //////////////////////////////////////////////////////////////////////// |
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| 238 | // SRCID definition |
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| 239 | //////////////////////////////////////////////////////////////////////// |
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| 240 | // All initiators are in the same indexing space (14 bits). |
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| 241 | // The SRCID is structured in two fields: |
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[875] | 242 | // - The 8 MSB bits define the cluster index (left aligned) |
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| 243 | // - The 6 LSB bits define the local index. |
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[747] | 244 | // Two different initiators cannot have the same SRCID, but a given |
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| 245 | // initiator can have two alias SRCIDs: |
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| 246 | // - Internal initiators (procs, mdma) are replicated in all clusters, |
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| 247 | // and each initiator has one single SRCID. |
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| 248 | // - External initiators (bdev, cdma) are not replicated, but can be |
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| 249 | // accessed in 2 clusters : cluster_iob0 and cluster_iob1. |
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| 250 | // They have the same local index, but two different cluster indexes. |
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| 251 | // |
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| 252 | // As cluster_iob0 and cluster_iob1 contain both internal initiators |
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| 253 | // and external initiators, they must have different local indexes. |
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| 254 | // Consequence: For a local interconnect, the INI_ID port index |
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| 255 | // is NOT equal to the SRCID local index, and the local interconnect |
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| 256 | // must make a translation: SRCID => INI_ID |
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| 257 | //////////////////////////////////////////////////////////////////////// |
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| 258 | |
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| 259 | #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 |
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| 260 | #define MDMA_LOCAL_SRCID 0x8 |
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| 261 | #define IOBX_LOCAL_SRCID 0x9 |
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| 262 | #define MEMC_LOCAL_SRCID 0xA |
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| 263 | #define CDMA_LOCAL_SRCID 0xB |
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| 264 | #define BDEV_LOCAL_SRCID 0xC |
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| 265 | #define IOPI_LOCAL_SRCID 0xD |
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| 266 | |
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| 267 | /////////////////////////////////////////////////////////////////////// |
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| 268 | // TGT_ID and INI_ID port indexing for INT local interconnect |
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| 269 | /////////////////////////////////////////////////////////////////////// |
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| 270 | |
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| 271 | #define INT_MEMC_TGT_ID 0 |
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| 272 | #define INT_XICU_TGT_ID 1 |
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| 273 | #define INT_MDMA_TGT_ID 2 |
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[748] | 274 | #define INT_BROM_TGT_ID 3 |
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| 275 | #define INT_IOBX_TGT_ID 4 |
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[747] | 276 | |
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| 277 | #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) |
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| 278 | #define INT_MDMA_INI_ID (NB_PROCS_MAX) |
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| 279 | #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) |
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| 280 | |
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| 281 | /////////////////////////////////////////////////////////////////////// |
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| 282 | // TGT_ID and INI_ID port indexing for RAM local interconnect |
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| 283 | /////////////////////////////////////////////////////////////////////// |
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| 284 | |
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| 285 | #define RAM_XRAM_TGT_ID 0 |
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| 286 | |
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| 287 | #define RAM_MEMC_INI_ID 0 |
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| 288 | #define RAM_IOBX_INI_ID 1 |
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| 289 | |
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| 290 | /////////////////////////////////////////////////////////////////////// |
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| 291 | // TGT_ID and INI_ID port indexing for I0X local interconnect |
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| 292 | /////////////////////////////////////////////////////////////////////// |
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| 293 | |
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| 294 | #define IOX_FBUF_TGT_ID 0 |
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| 295 | #define IOX_BDEV_TGT_ID 1 |
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| 296 | #define IOX_MNIC_TGT_ID 2 |
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| 297 | #define IOX_CDMA_TGT_ID 3 |
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[748] | 298 | #define IOX_MTTY_TGT_ID 4 |
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| 299 | #define IOX_IOPI_TGT_ID 5 |
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[769] | 300 | #define IOX_SIMH_TGT_ID 6 |
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| 301 | #define IOX_IOB0_TGT_ID 7 |
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| 302 | #define IOX_IOB1_TGT_ID 8 |
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[747] | 303 | |
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| 304 | #define IOX_BDEV_INI_ID 0 |
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| 305 | #define IOX_CDMA_INI_ID 1 |
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| 306 | #define IOX_IOPI_INI_ID 2 |
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| 307 | #define IOX_IOB0_INI_ID 3 |
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| 308 | #define IOX_IOB1_INI_ID 4 |
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| 309 | |
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| 310 | //////////////////////////////////////////////////////////////////////// |
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| 311 | int _main(int argc, char *argv[]) |
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| 312 | //////////////////////////////////////////////////////////////////////// |
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| 313 | { |
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| 314 | using namespace sc_core; |
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| 315 | using namespace soclib::caba; |
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| 316 | using namespace soclib::common; |
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| 317 | |
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| 318 | |
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[859] | 319 | char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code |
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| 320 | size_t ncycles = UINT_MAX; // simulated cycles |
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| 321 | char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image |
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| 322 | ssize_t threads_nr = 1; // simulator's threads number |
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| 323 | size_t faulty_mask = 0x1F; // interface mask for the faulty router |
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| 324 | bool debug_ok = false; // trace activated |
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| 325 | size_t debug_period = 1; // trace period |
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| 326 | size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc |
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| 327 | size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc |
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| 328 | size_t debug_xram_id = 0xFFFFFFFF; // index of traced xram |
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| 329 | bool debug_iob = false; // trace iob0 & iob1 when true |
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| 330 | uint32_t debug_from = 0; // trace start cycle |
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| 331 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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[747] | 332 | |
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[889] | 333 | std::vector<size_t> faulty_routers; |
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| 334 | |
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[747] | 335 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
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| 336 | "ERROR: we must have X_WIDTH == Y_WIDTH == 4"); |
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| 337 | |
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| 338 | ////////////// command line arguments ////////////////////// |
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| 339 | if (argc > 1) |
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| 340 | { |
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| 341 | for (int n = 1; n < argc; n = n + 2) |
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| 342 | { |
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[855] | 343 | if ((strcmp(argv[n], "-NCYCLES") == 0) && (n+1<argc)) |
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[747] | 344 | { |
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[748] | 345 | ncycles = strtol(argv[n+1], NULL, 0); |
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[747] | 346 | } |
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[855] | 347 | else if ((strcmp(argv[n], "-SOFT") == 0) && (n+1<argc) ) |
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[747] | 348 | { |
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| 349 | strcpy(soft_name, argv[n+1]); |
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| 350 | } |
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[855] | 351 | else if ((strcmp(argv[n], "-DEBUG") == 0) && (n+1<argc) ) |
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[747] | 352 | { |
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| 353 | debug_ok = true; |
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[748] | 354 | debug_from = strtol(argv[n+1], NULL, 0); |
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[747] | 355 | } |
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[855] | 356 | else if ((strcmp(argv[n], "-DISK") == 0) && (n+1<argc) ) |
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[747] | 357 | { |
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| 358 | strcpy(disk_name, argv[n+1]); |
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| 359 | } |
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[855] | 360 | else if ((strcmp(argv[n], "-MEMCID") == 0) && (n+1<argc) ) |
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[747] | 361 | { |
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[748] | 362 | debug_memc_id = strtol(argv[n+1], NULL, 0); |
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[855] | 363 | size_t x = debug_memc_id >> Y_WIDTH; |
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| 364 | size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); |
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[806] | 365 | if( (x>=X_SIZE) || (y>=Y_SIZE) ) |
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[747] | 366 | { |
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[806] | 367 | std::cout << "MEMCID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; |
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[747] | 368 | exit(0); |
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| 369 | } |
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| 370 | } |
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[855] | 371 | else if ((strcmp(argv[n], "-XRAMID") == 0) && (n+1<argc) ) |
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[747] | 372 | { |
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[748] | 373 | debug_xram_id = strtol(argv[n+1], NULL, 0); |
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[855] | 374 | size_t x = debug_xram_id >> Y_WIDTH; |
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| 375 | size_t y = debug_xram_id & ((1 << Y_WIDTH) - 1); |
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[806] | 376 | if( (x>=X_SIZE) || (y>=Y_SIZE) ) |
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[747] | 377 | { |
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[806] | 378 | std::cout << "XRAMID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; |
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[747] | 379 | exit(0); |
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| 380 | } |
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| 381 | } |
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[855] | 382 | else if ((strcmp(argv[n], "-IOB") == 0) && (n+1<argc) ) |
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[747] | 383 | { |
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[748] | 384 | debug_iob = strtol(argv[n+1], NULL, 0); |
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[747] | 385 | } |
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[855] | 386 | else if ((strcmp(argv[n], "-PROCID") == 0) && (n+1<argc) ) |
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[747] | 387 | { |
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[748] | 388 | debug_proc_id = strtol(argv[n+1], NULL, 0); |
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[855] | 389 | size_t cluster_xy = debug_proc_id >> P_WIDTH; |
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| 390 | size_t x = cluster_xy >> Y_WIDTH; |
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| 391 | size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); |
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[806] | 392 | if( (x>=X_SIZE) || (y>=Y_SIZE) ) |
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[747] | 393 | { |
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[806] | 394 | std::cout << "PROCID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; |
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[747] | 395 | exit(0); |
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| 396 | } |
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| 397 | } |
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| 398 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) |
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| 399 | { |
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[748] | 400 | threads_nr = strtol(argv[n+1], NULL, 0); |
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[747] | 401 | threads_nr = (threads_nr < 1) ? 1 : threads_nr; |
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| 402 | } |
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| 403 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
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| 404 | { |
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[748] | 405 | frozen_cycles = strtol(argv[n+1], NULL, 0); |
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[747] | 406 | } |
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| 407 | else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) |
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| 408 | { |
---|
[748] | 409 | debug_period = strtol(argv[n+1], NULL, 0); |
---|
[747] | 410 | } |
---|
[904] | 411 | else if ((strcmp(argv[n], "-FAULTY_ROUTER") == 0) && (n+3 < argc) ) |
---|
[855] | 412 | { |
---|
[904] | 413 | size_t t = strtol(argv[n+1], NULL, 0); |
---|
| 414 | size_t x = strtol(argv[n+2], NULL, 0); |
---|
| 415 | size_t y = strtol(argv[n+3], NULL, 0); |
---|
| 416 | n+=2; |
---|
| 417 | if( (t > 4) ) |
---|
| 418 | { |
---|
| 419 | std::cout << "FAULTY_ROUTER NoC index is too big (index > 4)" << std::endl; |
---|
| 420 | exit(0); |
---|
| 421 | } |
---|
[855] | 422 | if( (x>=X_SIZE) || (y>=Y_SIZE) ) |
---|
| 423 | { |
---|
| 424 | std::cout << "FAULTY_ROUTER parameter doesn't fit X_SIZE/Y_SIZE" << std::endl; |
---|
| 425 | exit(0); |
---|
| 426 | } |
---|
[904] | 427 | faulty_routers.push_back((t << (X_WIDTH + Y_WIDTH)) | |
---|
| 428 | (x << (Y_WIDTH)) | |
---|
| 429 | (y)); |
---|
[855] | 430 | } |
---|
[859] | 431 | else if ((strcmp(argv[n], "-FAULTY_MASK") == 0) && (n+1 < argc) ) |
---|
| 432 | { |
---|
| 433 | faulty_mask = strtol(argv[n+1], NULL, 0); |
---|
| 434 | if( faulty_mask > 0x1F ) |
---|
| 435 | { |
---|
| 436 | std::cout << "FAULTY_MASK parameter max value is 0x1F" << std::endl; |
---|
| 437 | exit(0); |
---|
| 438 | } |
---|
| 439 | } |
---|
[747] | 440 | else |
---|
| 441 | { |
---|
[855] | 442 | std::cout << " Arguments are (key, value) couples." << std::endl; |
---|
[747] | 443 | std::cout << " The order is not important." << std::endl; |
---|
| 444 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
---|
| 445 | std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; |
---|
| 446 | std::cout << " -DISK pathname_for_disk_image" << std::endl; |
---|
| 447 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
---|
| 448 | std::cout << " -DEBUG debug_start_cycle" << std::endl; |
---|
| 449 | std::cout << " -THREADS simulator's threads number" << std::endl; |
---|
| 450 | std::cout << " -FROZEN max_number_of_lines" << std::endl; |
---|
| 451 | std::cout << " -PERIOD number_of_cycles between trace" << std::endl; |
---|
| 452 | std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; |
---|
| 453 | std::cout << " -XRAMID index_xram_to_be_traced" << std::endl; |
---|
| 454 | std::cout << " -PROCID index_proc_to_be_traced" << std::endl; |
---|
| 455 | std::cout << " -IOB non_zero_value" << std::endl; |
---|
| 456 | exit(0); |
---|
| 457 | } |
---|
| 458 | } |
---|
| 459 | } |
---|
| 460 | |
---|
[748] | 461 | // Activate Distributed Boot (set by environment variable) |
---|
| 462 | // When this is activated, every processor boots with its instruction and data |
---|
| 463 | // physical address extension register initialized to its cluster index |
---|
| 464 | // (X_LOCAL, Y_LOCAL). To support this feature, a distributed ROM is |
---|
| 465 | // implemented in each cluster. |
---|
| 466 | |
---|
| 467 | const bool distributed_boot = (getenv("DISTRIBUTED_BOOT") != NULL); |
---|
| 468 | |
---|
[747] | 469 | // checking hardware parameters |
---|
[806] | 470 | assert( (X_SIZE <= (1 << X_WIDTH)) and |
---|
| 471 | "The X_SIZE parameter cannot be larger than 16" ); |
---|
[747] | 472 | |
---|
[806] | 473 | assert( (Y_SIZE <= (1 << Y_WIDTH)) and |
---|
| 474 | "The Y_SIZE parameter cannot be larger than 16" ); |
---|
[747] | 475 | |
---|
[875] | 476 | assert( (NB_PROCS_MAX <= (1 << P_WIDTH)) and |
---|
| 477 | "NB_PROCS_MAX parameter cannot be larger than 2^P_WIDTH" ); |
---|
[747] | 478 | |
---|
| 479 | assert( (NB_DMA_CHANNELS <= 4) and |
---|
| 480 | "The NB_DMA_CHANNELS parameter cannot be larger than 4" ); |
---|
| 481 | |
---|
[875] | 482 | assert( (NB_TTY_CHANNELS >= 1) and (NB_TTY_CHANNELS <= 16) and |
---|
| 483 | "The NB_TTY_CHANNELS parameter cannot be larger than 16" ); |
---|
[747] | 484 | |
---|
| 485 | assert( (NB_NIC_CHANNELS == 2) and |
---|
| 486 | "The NB_NIC_CHANNELS parameter must be 2" ); |
---|
| 487 | |
---|
| 488 | std::cout << std::endl << std::dec |
---|
[806] | 489 | << " - X_SIZE = " << X_SIZE << std::endl |
---|
| 490 | << " - Y_SIZE = " << Y_SIZE << std::endl |
---|
[747] | 491 | << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl |
---|
| 492 | << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl |
---|
| 493 | << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl |
---|
| 494 | << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl |
---|
| 495 | << " - MEMC_WAYS = " << MEMC_WAYS << std::endl |
---|
| 496 | << " - MEMC_SETS = " << MEMC_SETS << std::endl |
---|
| 497 | << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl |
---|
| 498 | << " - MAX_FROZEN = " << frozen_cycles << std::endl |
---|
[748] | 499 | << " - DIST_BOOT = " << distributed_boot << std::endl |
---|
[747] | 500 | << " - DEBUG_PROCID = " << debug_proc_id << std::endl |
---|
| 501 | << " - DEBUG_MEMCID = " << debug_memc_id << std::endl |
---|
| 502 | << " - DEBUG_XRAMID = " << debug_xram_id << std::endl; |
---|
| 503 | |
---|
| 504 | std::cout << std::endl; |
---|
| 505 | |
---|
| 506 | #if USE_OPENMP |
---|
| 507 | omp_set_dynamic(false); |
---|
| 508 | omp_set_num_threads(threads_nr); |
---|
[906] | 509 | std::cerr << "Built with openmp version " << _OPENMP |
---|
| 510 | << " / numthreads = " << threads_nr << std::endl; |
---|
[747] | 511 | #endif |
---|
| 512 | |
---|
| 513 | // Define VciParams objects |
---|
| 514 | typedef soclib::caba::VciParams<vci_cell_width_int, |
---|
| 515 | vci_plen_width, |
---|
| 516 | vci_address_width, |
---|
| 517 | vci_rerror_width, |
---|
| 518 | vci_clen_width, |
---|
| 519 | vci_rflag_width, |
---|
| 520 | vci_srcid_width, |
---|
| 521 | vci_pktid_width, |
---|
| 522 | vci_trdid_width, |
---|
| 523 | vci_wrplen_width> vci_param_int; |
---|
| 524 | |
---|
| 525 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
---|
| 526 | vci_plen_width, |
---|
| 527 | vci_address_width, |
---|
| 528 | vci_rerror_width, |
---|
| 529 | vci_clen_width, |
---|
| 530 | vci_rflag_width, |
---|
| 531 | vci_srcid_width, |
---|
| 532 | vci_pktid_width, |
---|
| 533 | vci_trdid_width, |
---|
| 534 | vci_wrplen_width> vci_param_ext; |
---|
| 535 | |
---|
[859] | 536 | const size_t cluster_iob0 = cluster(0, 0); // cluster containing IOB0 |
---|
| 537 | const size_t cluster_iob1 = cluster(X_SIZE-1, Y_SIZE-1); // cluster containing IOB1 |
---|
| 538 | |
---|
[747] | 539 | ///////////////////////////////////////////////////////////////////// |
---|
| 540 | // INT network mapping table |
---|
| 541 | // - two levels address decoding for commands |
---|
| 542 | // - two levels srcid decoding for responses |
---|
| 543 | // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster |
---|
| 544 | // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster |
---|
| 545 | ///////////////////////////////////////////////////////////////////// |
---|
| 546 | MappingTable maptab_int( vci_address_width, |
---|
[806] | 547 | IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), |
---|
| 548 | IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), |
---|
[747] | 549 | 0x00FF000000); |
---|
| 550 | |
---|
[806] | 551 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 552 | { |
---|
[806] | 553 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
[747] | 554 | { |
---|
[855] | 555 | uint64_t offset = ((uint64_t)cluster(x, y)) |
---|
[806] | 556 | << (vci_address_width-X_WIDTH-Y_WIDTH); |
---|
[747] | 557 | bool config = true; |
---|
| 558 | bool cacheable = true; |
---|
| 559 | |
---|
| 560 | // the four following segments are defined in all clusters |
---|
| 561 | |
---|
| 562 | std::ostringstream smemc_conf; |
---|
| 563 | smemc_conf << "int_seg_memc_conf_" << x << "_" << y; |
---|
| 564 | maptab_int.add(Segment(smemc_conf.str(), SEG_MMC_BASE+offset, SEG_MMC_SIZE, |
---|
[855] | 565 | IntTab(cluster(x, y), INT_MEMC_TGT_ID), not cacheable, config )); |
---|
[747] | 566 | |
---|
| 567 | std::ostringstream smemc_xram; |
---|
| 568 | smemc_xram << "int_seg_memc_xram_" << x << "_" << y; |
---|
| 569 | maptab_int.add(Segment(smemc_xram.str(), SEG_RAM_BASE+offset, SEG_RAM_SIZE, |
---|
[855] | 570 | IntTab(cluster(x, y), INT_MEMC_TGT_ID), cacheable)); |
---|
[747] | 571 | |
---|
| 572 | std::ostringstream sxicu; |
---|
| 573 | sxicu << "int_seg_xicu_" << x << "_" << y; |
---|
| 574 | maptab_int.add(Segment(sxicu.str(), SEG_XCU_BASE+offset, SEG_XCU_SIZE, |
---|
[855] | 575 | IntTab(cluster(x, y), INT_XICU_TGT_ID), not cacheable)); |
---|
[747] | 576 | |
---|
| 577 | std::ostringstream smdma; |
---|
| 578 | smdma << "int_seg_mdma_" << x << "_" << y; |
---|
| 579 | maptab_int.add(Segment(smdma.str(), SEG_DMA_BASE+offset, SEG_DMA_SIZE, |
---|
[855] | 580 | IntTab(cluster(x, y), INT_MDMA_TGT_ID), not cacheable)); |
---|
[747] | 581 | |
---|
[748] | 582 | std::ostringstream sbrom; |
---|
| 583 | sbrom << "int_seg_brom_" << x << "_" << y; |
---|
| 584 | maptab_int.add(Segment(sbrom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, |
---|
[855] | 585 | IntTab(cluster(x, y), INT_BROM_TGT_ID), cacheable)); |
---|
[748] | 586 | |
---|
[747] | 587 | // the following segments are only defined in cluster_iob0 or in cluster_iob1 |
---|
| 588 | |
---|
[855] | 589 | if ( (cluster(x, y) == cluster_iob0) or (cluster(x, y) == cluster_iob1) ) |
---|
[747] | 590 | { |
---|
| 591 | std::ostringstream siobx; |
---|
| 592 | siobx << "int_seg_iobx_" << x << "_" << y; |
---|
| 593 | maptab_int.add(Segment(siobx.str(), SEG_IOB_BASE+offset, SEG_IOB_SIZE, |
---|
[855] | 594 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable, config )); |
---|
[747] | 595 | |
---|
| 596 | std::ostringstream stty; |
---|
| 597 | stty << "int_seg_mtty_" << x << "_" << y; |
---|
| 598 | maptab_int.add(Segment(stty.str(), SEG_TTY_BASE+offset, SEG_TTY_SIZE, |
---|
[855] | 599 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 600 | |
---|
| 601 | std::ostringstream sfbf; |
---|
| 602 | sfbf << "int_seg_fbuf_" << x << "_" << y; |
---|
| 603 | maptab_int.add(Segment(sfbf.str(), SEG_FBF_BASE+offset, SEG_FBF_SIZE, |
---|
[855] | 604 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 605 | |
---|
| 606 | std::ostringstream sbdv; |
---|
| 607 | sbdv << "int_seg_bdev_" << x << "_" << y; |
---|
| 608 | maptab_int.add(Segment(sbdv.str(), SEG_IOC_BASE+offset, SEG_IOC_SIZE, |
---|
[855] | 609 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 610 | |
---|
| 611 | std::ostringstream snic; |
---|
| 612 | snic << "int_seg_mnic_" << x << "_" << y; |
---|
| 613 | maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, |
---|
[855] | 614 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 615 | |
---|
| 616 | std::ostringstream sdma; |
---|
| 617 | sdma << "int_seg_cdma_" << x << "_" << y; |
---|
| 618 | maptab_int.add(Segment(sdma.str(), SEG_CMA_BASE+offset, SEG_CMA_SIZE, |
---|
[855] | 619 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 620 | |
---|
| 621 | std::ostringstream spic; |
---|
| 622 | spic << "int_seg_iopi_" << x << "_" << y; |
---|
| 623 | maptab_int.add(Segment(spic.str(), SEG_PIC_BASE+offset, SEG_PIC_SIZE, |
---|
[855] | 624 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[769] | 625 | |
---|
| 626 | std::ostringstream ssim; |
---|
| 627 | ssim << "int_seg_simh_" << x << "_" << y; |
---|
| 628 | maptab_int.add(Segment(ssim.str(), SEG_SIM_BASE+offset, SEG_SIM_SIZE, |
---|
[855] | 629 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 630 | } |
---|
| 631 | |
---|
| 632 | // This define the mapping between the SRCIDs |
---|
| 633 | // and the port index on the local interconnect. |
---|
| 634 | |
---|
[855] | 635 | maptab_int.srcid_map( IntTab( cluster(x, y), MDMA_LOCAL_SRCID ), |
---|
| 636 | IntTab( cluster(x, y), INT_MDMA_INI_ID ) ); |
---|
[747] | 637 | |
---|
[855] | 638 | maptab_int.srcid_map( IntTab( cluster(x, y), IOBX_LOCAL_SRCID ), |
---|
| 639 | IntTab( cluster(x, y), INT_IOBX_INI_ID ) ); |
---|
[747] | 640 | |
---|
[855] | 641 | maptab_int.srcid_map( IntTab( cluster(x, y), IOPI_LOCAL_SRCID ), |
---|
| 642 | IntTab( cluster(x, y), INT_IOBX_INI_ID ) ); |
---|
[747] | 643 | |
---|
| 644 | for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) |
---|
[855] | 645 | maptab_int.srcid_map( IntTab( cluster(x, y), PROC_LOCAL_SRCID+p ), |
---|
| 646 | IntTab( cluster(x, y), INT_PROC_INI_ID+p ) ); |
---|
[747] | 647 | } |
---|
| 648 | } |
---|
| 649 | std::cout << "INT network " << maptab_int << std::endl; |
---|
| 650 | |
---|
| 651 | ///////////////////////////////////////////////////////////////////////// |
---|
| 652 | // RAM network mapping table |
---|
| 653 | // - two levels address decoding for commands |
---|
| 654 | // - two levels srcid decoding for responses |
---|
| 655 | // - 2 local initiators (MEMC, IOBX) per cluster |
---|
| 656 | // (IOBX component only in cluster_iob0 and cluster_iob1) |
---|
| 657 | // - 1 local target (XRAM) per cluster |
---|
| 658 | //////////////////////////////////////////////////////////////////////// |
---|
| 659 | MappingTable maptab_ram( vci_address_width, |
---|
[806] | 660 | IntTab(X_WIDTH+Y_WIDTH, 0), |
---|
| 661 | IntTab(X_WIDTH+Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), |
---|
[747] | 662 | 0x00FF000000); |
---|
| 663 | |
---|
[806] | 664 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 665 | { |
---|
[806] | 666 | for (size_t y = 0; y < Y_SIZE ; y++) |
---|
[747] | 667 | { |
---|
[855] | 668 | uint64_t offset = ((uint64_t)cluster(x, y)) |
---|
[806] | 669 | << (vci_address_width-X_WIDTH-Y_WIDTH); |
---|
[747] | 670 | |
---|
| 671 | std::ostringstream sxram; |
---|
| 672 | sxram << "ext_seg_xram_" << x << "_" << y; |
---|
| 673 | maptab_ram.add(Segment(sxram.str(), SEG_RAM_BASE+offset, |
---|
[855] | 674 | SEG_RAM_SIZE, IntTab(cluster(x, y), RAM_XRAM_TGT_ID), false)); |
---|
[747] | 675 | } |
---|
| 676 | } |
---|
| 677 | |
---|
| 678 | // This define the mapping between the initiators SRCID |
---|
| 679 | // and the port index on the RAM local interconnect. |
---|
| 680 | // External initiator have two alias SRCID (iob0 / iob1) |
---|
| 681 | |
---|
| 682 | maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), |
---|
| 683 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 684 | |
---|
| 685 | maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), |
---|
| 686 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 687 | |
---|
| 688 | maptab_ram.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), |
---|
| 689 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 690 | |
---|
| 691 | maptab_ram.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), |
---|
| 692 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 693 | |
---|
| 694 | maptab_ram.srcid_map( IntTab( cluster_iob0, IOPI_LOCAL_SRCID ), |
---|
| 695 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 696 | |
---|
| 697 | maptab_ram.srcid_map( IntTab( cluster_iob1, IOPI_LOCAL_SRCID ), |
---|
| 698 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 699 | |
---|
| 700 | maptab_ram.srcid_map( IntTab( cluster_iob0, MEMC_LOCAL_SRCID ), |
---|
| 701 | IntTab( cluster_iob0, RAM_MEMC_INI_ID ) ); |
---|
| 702 | |
---|
| 703 | maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), |
---|
| 704 | IntTab( cluster_iob1, RAM_MEMC_INI_ID ) ); |
---|
| 705 | |
---|
| 706 | std::cout << "RAM network " << maptab_ram << std::endl; |
---|
| 707 | |
---|
| 708 | /////////////////////////////////////////////////////////////////////// |
---|
| 709 | // IOX network mapping table |
---|
| 710 | // - two levels address decoding for commands (9, 7) bits |
---|
| 711 | // - two levels srcid decoding for responses |
---|
| 712 | // - 5 initiators (IOB0, IOB1, BDEV, CDMA, IOPI) |
---|
| 713 | // - 9 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC, IOPI) |
---|
| 714 | // |
---|
| 715 | // Address bit 32 is used to determine if a command must be routed to |
---|
| 716 | // IOB0 or IOB1. |
---|
| 717 | /////////////////////////////////////////////////////////////////////// |
---|
| 718 | MappingTable maptab_iox( |
---|
| 719 | vci_address_width, |
---|
[806] | 720 | IntTab(X_WIDTH + Y_WIDTH - 1, 16 - X_WIDTH - Y_WIDTH + 1), |
---|
| 721 | IntTab(X_WIDTH + Y_WIDTH , vci_param_ext::S - X_WIDTH - Y_WIDTH), |
---|
[747] | 722 | 0x00FF000000); |
---|
| 723 | |
---|
| 724 | // External peripherals segments |
---|
| 725 | // When there is more than one cluster, external peripherals can be accessed |
---|
| 726 | // through two segments, depending on the used IOB (IOB0 or IOB1). |
---|
| 727 | |
---|
| 728 | const uint64_t iob0_base = ((uint64_t)cluster_iob0) |
---|
[806] | 729 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[747] | 730 | |
---|
| 731 | maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TTY_BASE + iob0_base, SEG_TTY_SIZE, |
---|
| 732 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
| 733 | maptab_iox.add(Segment("iox_seg_fbuf_0", SEG_FBF_BASE + iob0_base, SEG_FBF_SIZE, |
---|
| 734 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
| 735 | maptab_iox.add(Segment("iox_seg_bdev_0", SEG_IOC_BASE + iob0_base, SEG_IOC_SIZE, |
---|
| 736 | IntTab(0, IOX_BDEV_TGT_ID), false)); |
---|
| 737 | maptab_iox.add(Segment("iox_seg_mnic_0", SEG_NIC_BASE + iob0_base, SEG_NIC_SIZE, |
---|
| 738 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
| 739 | maptab_iox.add(Segment("iox_seg_cdma_0", SEG_CMA_BASE + iob0_base, SEG_CMA_SIZE, |
---|
| 740 | IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
| 741 | maptab_iox.add(Segment("iox_seg_iopi_0", SEG_PIC_BASE + iob0_base, SEG_PIC_SIZE, |
---|
| 742 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
[769] | 743 | maptab_iox.add(Segment("iox_seg_simh_0", SEG_SIM_BASE + iob0_base, SEG_SIM_SIZE, |
---|
| 744 | IntTab(0, IOX_SIMH_TGT_ID), false)); |
---|
[747] | 745 | |
---|
| 746 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 747 | { |
---|
| 748 | const uint64_t iob1_base = ((uint64_t)cluster_iob1) |
---|
[806] | 749 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[747] | 750 | |
---|
| 751 | maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TTY_BASE + iob1_base, SEG_TTY_SIZE, |
---|
| 752 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
| 753 | maptab_iox.add(Segment("iox_seg_fbuf_1", SEG_FBF_BASE + iob1_base, SEG_FBF_SIZE, |
---|
| 754 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
| 755 | maptab_iox.add(Segment("iox_seg_bdev_1", SEG_IOC_BASE + iob1_base, SEG_IOC_SIZE, |
---|
| 756 | IntTab(0, IOX_BDEV_TGT_ID), false)); |
---|
| 757 | maptab_iox.add(Segment("iox_seg_mnic_1", SEG_NIC_BASE + iob1_base, SEG_NIC_SIZE, |
---|
| 758 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
| 759 | maptab_iox.add(Segment("iox_seg_cdma_1", SEG_CMA_BASE + iob1_base, SEG_CMA_SIZE, |
---|
| 760 | IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
| 761 | maptab_iox.add(Segment("iox_seg_iopi_1", SEG_PIC_BASE + iob1_base, SEG_PIC_SIZE, |
---|
| 762 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
[769] | 763 | maptab_iox.add(Segment("iox_seg_simh_1", SEG_SIM_BASE + iob1_base, SEG_SIM_SIZE, |
---|
| 764 | IntTab(0, IOX_SIMH_TGT_ID), false)); |
---|
[747] | 765 | } |
---|
| 766 | |
---|
| 767 | // If there is more than one cluster, external peripherals |
---|
| 768 | // can access RAM through two segments (IOB0 / IOB1). |
---|
| 769 | // As IOMMU is not activated, addresses are 40 bits (physical addresses), |
---|
| 770 | // and the choice depends on address bit A[32]. |
---|
[806] | 771 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 772 | { |
---|
[806] | 773 | for (size_t y = 0; y < Y_SIZE ; y++) |
---|
[747] | 774 | { |
---|
| 775 | const bool wti = true; |
---|
| 776 | const bool cacheable = true; |
---|
| 777 | |
---|
[855] | 778 | const uint64_t offset = ((uint64_t)cluster(x, y)) |
---|
[806] | 779 | << (vci_address_width-X_WIDTH-Y_WIDTH); |
---|
[747] | 780 | |
---|
| 781 | const uint64_t xicu_base = SEG_XCU_BASE + offset; |
---|
| 782 | |
---|
| 783 | if ( (y & 0x1) == 0 ) // use IOB0 |
---|
| 784 | { |
---|
| 785 | std::ostringstream sxcu0; |
---|
| 786 | sxcu0 << "iox_seg_xcu0_" << x << "_" << y; |
---|
| 787 | maptab_iox.add(Segment(sxcu0.str(), xicu_base, SEG_XCU_SIZE, |
---|
| 788 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, wti)); |
---|
| 789 | |
---|
| 790 | std::ostringstream siob0; |
---|
| 791 | siob0 << "iox_seg_ram0_" << x << "_" << y; |
---|
| 792 | maptab_iox.add(Segment(siob0.str(), offset, SEG_XCU_BASE, |
---|
| 793 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not wti)); |
---|
| 794 | } |
---|
| 795 | else // USE IOB1 |
---|
| 796 | { |
---|
| 797 | std::ostringstream sxcu1; |
---|
| 798 | sxcu1 << "iox_seg_xcu1_" << x << "_" << y; |
---|
| 799 | maptab_iox.add(Segment(sxcu1.str(), xicu_base, SEG_XCU_SIZE, |
---|
| 800 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, wti)); |
---|
| 801 | |
---|
| 802 | std::ostringstream siob1; |
---|
| 803 | siob1 << "iox_seg_ram1_" << x << "_" << y; |
---|
| 804 | maptab_iox.add(Segment(siob1.str(), offset, SEG_XCU_BASE, |
---|
| 805 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not wti)); |
---|
| 806 | } |
---|
| 807 | } |
---|
| 808 | } |
---|
| 809 | |
---|
| 810 | // This define the mapping between the external initiators (SRCID) |
---|
| 811 | // and the port index on the IOX local interconnect. |
---|
| 812 | |
---|
| 813 | maptab_iox.srcid_map( IntTab( 0, CDMA_LOCAL_SRCID ) , |
---|
| 814 | IntTab( 0, IOX_CDMA_INI_ID ) ); |
---|
| 815 | maptab_iox.srcid_map( IntTab( 0, BDEV_LOCAL_SRCID ) , |
---|
| 816 | IntTab( 0, IOX_BDEV_INI_ID ) ); |
---|
| 817 | maptab_iox.srcid_map( IntTab( 0, IOPI_LOCAL_SRCID ) , |
---|
| 818 | IntTab( 0, IOX_IOPI_INI_ID ) ); |
---|
| 819 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB0_INI_ID ) , |
---|
| 820 | IntTab( 0, IOX_IOB0_INI_ID ) ); |
---|
| 821 | |
---|
| 822 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 823 | { |
---|
| 824 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB1_INI_ID ) , |
---|
| 825 | IntTab( 0, IOX_IOB1_INI_ID ) ); |
---|
| 826 | } |
---|
| 827 | |
---|
| 828 | std::cout << "IOX network " << maptab_iox << std::endl; |
---|
| 829 | |
---|
| 830 | //////////////////// |
---|
| 831 | // Signals |
---|
| 832 | /////////////////// |
---|
| 833 | |
---|
| 834 | sc_clock signal_clk("clk"); |
---|
| 835 | sc_signal<bool> signal_resetn("resetn"); |
---|
| 836 | |
---|
| 837 | sc_signal<bool> signal_irq_false; |
---|
| 838 | sc_signal<bool> signal_irq_bdev; |
---|
[875] | 839 | sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS]; |
---|
[747] | 840 | sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; |
---|
| 841 | sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; |
---|
| 842 | sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS]; |
---|
| 843 | |
---|
| 844 | // VCI signals for IOX network |
---|
| 845 | VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); |
---|
| 846 | VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); |
---|
| 847 | VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev"); |
---|
| 848 | VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma"); |
---|
| 849 | VciSignals<vci_param_ext> signal_vci_ini_iopi("signal_vci_ini_iopi"); |
---|
| 850 | |
---|
| 851 | VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); |
---|
| 852 | VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); |
---|
| 853 | VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
---|
| 854 | VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
---|
| 855 | VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
---|
| 856 | VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev"); |
---|
| 857 | VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); |
---|
| 858 | VciSignals<vci_param_ext> signal_vci_tgt_iopi("signal_vci_ini_iopi"); |
---|
[769] | 859 | VciSignals<vci_param_ext> signal_vci_tgt_simh("signal_vci_ini_simh"); |
---|
[747] | 860 | |
---|
| 861 | // Horizontal inter-clusters INT network DSPIN |
---|
| 862 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc = |
---|
[806] | 863 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", X_SIZE-1, Y_SIZE, 3); |
---|
[747] | 864 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec = |
---|
[806] | 865 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", X_SIZE-1, Y_SIZE, 3); |
---|
[747] | 866 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc = |
---|
[806] | 867 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", X_SIZE-1, Y_SIZE, 2); |
---|
[747] | 868 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_dec = |
---|
[806] | 869 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_dec", X_SIZE-1, Y_SIZE, 2); |
---|
[747] | 870 | |
---|
| 871 | // Vertical inter-clusters INT network DSPIN |
---|
| 872 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc = |
---|
[806] | 873 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", X_SIZE, Y_SIZE-1, 3); |
---|
[747] | 874 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec = |
---|
[806] | 875 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", X_SIZE, Y_SIZE-1, 3); |
---|
[747] | 876 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc = |
---|
[806] | 877 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", X_SIZE, Y_SIZE-1, 2); |
---|
[747] | 878 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_dec = |
---|
[806] | 879 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_dec", X_SIZE, Y_SIZE-1, 2); |
---|
[747] | 880 | |
---|
| 881 | // Mesh boundaries INT network DSPIN |
---|
[751] | 882 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in = |
---|
[806] | 883 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", X_SIZE, Y_SIZE, 4, 3); |
---|
[751] | 884 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out = |
---|
[806] | 885 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", X_SIZE, Y_SIZE, 4, 3); |
---|
[751] | 886 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in = |
---|
[806] | 887 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", X_SIZE, Y_SIZE, 4, 2); |
---|
[751] | 888 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out = |
---|
[806] | 889 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", X_SIZE, Y_SIZE, 4, 2); |
---|
[747] | 890 | |
---|
[751] | 891 | |
---|
[747] | 892 | // Horizontal inter-clusters RAM network DSPIN |
---|
| 893 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = |
---|
[806] | 894 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_inc", X_SIZE-1, Y_SIZE); |
---|
[747] | 895 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = |
---|
[806] | 896 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_dec", X_SIZE-1, Y_SIZE); |
---|
[747] | 897 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = |
---|
[806] | 898 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_inc", X_SIZE-1, Y_SIZE); |
---|
[747] | 899 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = |
---|
[806] | 900 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_dec", X_SIZE-1, Y_SIZE); |
---|
[747] | 901 | |
---|
| 902 | // Vertical inter-clusters RAM network DSPIN |
---|
| 903 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = |
---|
[806] | 904 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_inc", X_SIZE, Y_SIZE-1); |
---|
[747] | 905 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = |
---|
[806] | 906 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_dec", X_SIZE, Y_SIZE-1); |
---|
[747] | 907 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = |
---|
[806] | 908 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_inc", X_SIZE, Y_SIZE-1); |
---|
[747] | 909 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = |
---|
[806] | 910 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_dec", X_SIZE, Y_SIZE-1); |
---|
[747] | 911 | |
---|
| 912 | // Mesh boundaries RAM network DSPIN |
---|
[751] | 913 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = |
---|
[806] | 914 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_in", X_SIZE, Y_SIZE, 4); |
---|
[751] | 915 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = |
---|
[806] | 916 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_out", X_SIZE, Y_SIZE, 4); |
---|
[751] | 917 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = |
---|
[806] | 918 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_in", X_SIZE, Y_SIZE, 4); |
---|
[751] | 919 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = |
---|
[806] | 920 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_out", X_SIZE, Y_SIZE, 4); |
---|
[747] | 921 | |
---|
| 922 | //////////////////////////// |
---|
| 923 | // Loader |
---|
| 924 | //////////////////////////// |
---|
| 925 | |
---|
| 926 | #if USE_ALMOS |
---|
| 927 | soclib::common::Loader loader(almos_bootloader_pathname, |
---|
| 928 | almos_archinfo_pathname, |
---|
| 929 | almos_kernel_pathname); |
---|
| 930 | #else |
---|
| 931 | soclib::common::Loader loader(soft_name); |
---|
| 932 | #endif |
---|
| 933 | |
---|
[756] | 934 | // initialize memory with a value different than 0 (expose software errors |
---|
| 935 | // dues to uninitialized data) |
---|
| 936 | loader.memory_default(0xA0); |
---|
| 937 | |
---|
[747] | 938 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 939 | proc_iss::set_loader(loader); |
---|
| 940 | |
---|
| 941 | //////////////////////////////////////// |
---|
| 942 | // Instanciated Hardware Components |
---|
| 943 | //////////////////////////////////////// |
---|
| 944 | |
---|
| 945 | std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; |
---|
| 946 | |
---|
| 947 | const size_t nb_iox_initiators = (cluster_iob0 != cluster_iob1) ? 5 : 4; |
---|
[769] | 948 | const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 9 : 8; |
---|
[747] | 949 | |
---|
| 950 | // IOX network |
---|
| 951 | VciIoxNetwork<vci_param_ext>* iox_network; |
---|
| 952 | iox_network = new VciIoxNetwork<vci_param_ext>( "iox_network", |
---|
| 953 | maptab_iox, |
---|
| 954 | nb_iox_targets, |
---|
| 955 | nb_iox_initiators ); |
---|
[748] | 956 | |
---|
[747] | 957 | // Network Controller |
---|
| 958 | VciMultiNic<vci_param_ext>* mnic; |
---|
| 959 | mnic = new VciMultiNic<vci_param_ext>( "mnic", |
---|
| 960 | IntTab(0, IOX_MNIC_TGT_ID), |
---|
| 961 | maptab_iox, |
---|
| 962 | NB_NIC_CHANNELS, |
---|
[916] | 963 | 0, // mac_4 address |
---|
| 964 | 0, // mac_2 address |
---|
| 965 | 1 ); // NIC_MODE_SYNTHESIS |
---|
[747] | 966 | |
---|
| 967 | // Frame Buffer |
---|
| 968 | VciFrameBuffer<vci_param_ext>* fbuf; |
---|
| 969 | fbuf = new VciFrameBuffer<vci_param_ext>( "fbuf", |
---|
| 970 | IntTab(0, IOX_FBUF_TGT_ID), |
---|
| 971 | maptab_iox, |
---|
| 972 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
---|
| 973 | |
---|
| 974 | // Block Device |
---|
| 975 | // for AHCI |
---|
| 976 | // std::vector<std::string> filenames; |
---|
| 977 | // filenames.push_back(disk_name); // one single disk |
---|
| 978 | VciBlockDeviceTsar<vci_param_ext>* bdev; |
---|
| 979 | bdev = new VciBlockDeviceTsar<vci_param_ext>( "bdev", |
---|
| 980 | maptab_iox, |
---|
| 981 | IntTab(0, BDEV_LOCAL_SRCID), |
---|
| 982 | IntTab(0, IOX_BDEV_TGT_ID), |
---|
| 983 | disk_name, |
---|
| 984 | 512, // block size |
---|
| 985 | 64, // burst size (bytes) |
---|
| 986 | 0 ); // disk latency |
---|
| 987 | |
---|
| 988 | // Chained Buffer DMA controller |
---|
| 989 | VciChbufDma<vci_param_ext>* cdma; |
---|
| 990 | cdma = new VciChbufDma<vci_param_ext>( "cdma", |
---|
| 991 | maptab_iox, |
---|
| 992 | IntTab(0, CDMA_LOCAL_SRCID), |
---|
| 993 | IntTab(0, IOX_CDMA_TGT_ID), |
---|
| 994 | 64, // burst size (bytes) |
---|
| 995 | 2*NB_NIC_CHANNELS ); |
---|
| 996 | // Multi-TTY controller |
---|
| 997 | std::vector<std::string> vect_names; |
---|
| 998 | for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ ) |
---|
| 999 | { |
---|
| 1000 | std::ostringstream term_name; |
---|
| 1001 | term_name << "term" << tid; |
---|
| 1002 | vect_names.push_back(term_name.str().c_str()); |
---|
| 1003 | } |
---|
| 1004 | VciMultiTty<vci_param_ext>* mtty; |
---|
| 1005 | mtty = new VciMultiTty<vci_param_ext>( "mtty", |
---|
| 1006 | IntTab(0, IOX_MTTY_TGT_ID), |
---|
| 1007 | maptab_iox, |
---|
| 1008 | vect_names); |
---|
| 1009 | |
---|
| 1010 | // IOPIC |
---|
| 1011 | VciIopic<vci_param_ext>* iopi; |
---|
| 1012 | iopi = new VciIopic<vci_param_ext>( "iopi", |
---|
| 1013 | maptab_iox, |
---|
| 1014 | IntTab(0, IOPI_LOCAL_SRCID), |
---|
| 1015 | IntTab(0, IOX_IOPI_TGT_ID), |
---|
| 1016 | 32 ); // number of input HWI |
---|
[748] | 1017 | |
---|
[769] | 1018 | // Simhelper |
---|
| 1019 | VciSimhelper<vci_param_ext>* simh; |
---|
| 1020 | simh = new VciSimhelper<vci_param_ext>("simh", |
---|
| 1021 | IntTab(0, IOX_SIMH_TGT_ID), |
---|
| 1022 | maptab_iox ); |
---|
| 1023 | |
---|
[747] | 1024 | // Clusters |
---|
| 1025 | TsarIobCluster<vci_param_int, |
---|
| 1026 | vci_param_ext, |
---|
| 1027 | dspin_int_cmd_width, |
---|
| 1028 | dspin_int_rsp_width, |
---|
| 1029 | dspin_ram_cmd_width, |
---|
[806] | 1030 | dspin_ram_rsp_width>* clusters[X_SIZE][Y_SIZE]; |
---|
[747] | 1031 | |
---|
| 1032 | #if USE_OPENMP |
---|
| 1033 | #pragma omp parallel |
---|
| 1034 | { |
---|
| 1035 | #pragma omp for |
---|
| 1036 | #endif |
---|
[806] | 1037 | for(size_t i = 0; i < (X_SIZE * Y_SIZE); i++) |
---|
[747] | 1038 | { |
---|
[806] | 1039 | size_t x = i / Y_SIZE; |
---|
| 1040 | size_t y = i % Y_SIZE; |
---|
[747] | 1041 | |
---|
| 1042 | #if USE_OPENMP |
---|
| 1043 | #pragma omp critical |
---|
| 1044 | { |
---|
| 1045 | #endif |
---|
| 1046 | std::cout << std::endl; |
---|
| 1047 | std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; |
---|
| 1048 | std::cout << std::endl; |
---|
| 1049 | |
---|
[855] | 1050 | const bool is_iob0 = (cluster(x, y) == cluster_iob0); |
---|
| 1051 | const bool is_iob1 = (cluster(x, y) == cluster_iob1); |
---|
[747] | 1052 | const bool is_io_cluster = is_iob0 || is_iob1; |
---|
| 1053 | |
---|
| 1054 | const int iox_iob_ini_id = is_iob0 ? |
---|
| 1055 | IOX_IOB0_INI_ID : |
---|
| 1056 | IOX_IOB1_INI_ID ; |
---|
| 1057 | const int iox_iob_tgt_id = is_iob0 ? |
---|
| 1058 | IOX_IOB0_TGT_ID : |
---|
| 1059 | IOX_IOB1_TGT_ID ; |
---|
| 1060 | |
---|
| 1061 | std::ostringstream sc; |
---|
| 1062 | sc << "cluster_" << x << "_" << y; |
---|
| 1063 | clusters[x][y] = new TsarIobCluster<vci_param_int, |
---|
| 1064 | vci_param_ext, |
---|
| 1065 | dspin_int_cmd_width, |
---|
| 1066 | dspin_int_rsp_width, |
---|
| 1067 | dspin_ram_cmd_width, |
---|
| 1068 | dspin_ram_rsp_width> |
---|
| 1069 | ( |
---|
| 1070 | sc.str().c_str(), |
---|
| 1071 | NB_PROCS_MAX, |
---|
| 1072 | NB_DMA_CHANNELS, |
---|
| 1073 | x, |
---|
| 1074 | y, |
---|
[806] | 1075 | X_SIZE, |
---|
| 1076 | Y_SIZE, |
---|
[747] | 1077 | |
---|
[806] | 1078 | P_WIDTH, |
---|
| 1079 | |
---|
[747] | 1080 | maptab_int, |
---|
| 1081 | maptab_ram, |
---|
| 1082 | maptab_iox, |
---|
| 1083 | |
---|
[806] | 1084 | X_WIDTH, |
---|
| 1085 | Y_WIDTH, |
---|
| 1086 | vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width, |
---|
[747] | 1087 | |
---|
| 1088 | INT_MEMC_TGT_ID, |
---|
| 1089 | INT_XICU_TGT_ID, |
---|
| 1090 | INT_MDMA_TGT_ID, |
---|
[748] | 1091 | INT_BROM_TGT_ID, |
---|
[747] | 1092 | INT_IOBX_TGT_ID, |
---|
| 1093 | |
---|
| 1094 | INT_PROC_INI_ID, |
---|
| 1095 | INT_MDMA_INI_ID, |
---|
| 1096 | INT_IOBX_INI_ID, |
---|
| 1097 | |
---|
| 1098 | RAM_XRAM_TGT_ID, |
---|
| 1099 | |
---|
| 1100 | RAM_MEMC_INI_ID, |
---|
| 1101 | RAM_IOBX_INI_ID, |
---|
| 1102 | |
---|
| 1103 | is_io_cluster, |
---|
| 1104 | iox_iob_tgt_id, |
---|
| 1105 | iox_iob_ini_id, |
---|
| 1106 | |
---|
| 1107 | MEMC_WAYS, |
---|
| 1108 | MEMC_SETS, |
---|
| 1109 | L1_IWAYS, |
---|
| 1110 | L1_ISETS, |
---|
| 1111 | L1_DWAYS, |
---|
| 1112 | L1_DSETS, |
---|
| 1113 | XRAM_LATENCY, |
---|
| 1114 | XCU_NB_INPUTS, |
---|
| 1115 | |
---|
[748] | 1116 | distributed_boot, |
---|
| 1117 | |
---|
[747] | 1118 | loader, |
---|
| 1119 | |
---|
| 1120 | frozen_cycles, |
---|
| 1121 | debug_from, |
---|
[855] | 1122 | debug_ok and (cluster(x, y) == debug_memc_id), |
---|
| 1123 | debug_ok and (cluster(x, y) == (debug_proc_id >> P_WIDTH)), |
---|
[747] | 1124 | debug_ok and debug_iob |
---|
| 1125 | ); |
---|
| 1126 | |
---|
| 1127 | #if USE_OPENMP |
---|
| 1128 | } // end critical |
---|
| 1129 | #endif |
---|
| 1130 | } // end for |
---|
| 1131 | #if USE_OPENMP |
---|
| 1132 | } |
---|
| 1133 | #endif |
---|
| 1134 | |
---|
[904] | 1135 | // disable all interfaces of the faulty CMD routers |
---|
| 1136 | std::cout << "\n*** List of deactivated routers ***\n"; |
---|
[889] | 1137 | for (std::vector<size_t>::iterator it = faulty_routers.begin(); |
---|
| 1138 | it != faulty_routers.end(); |
---|
| 1139 | ++it) |
---|
[855] | 1140 | { |
---|
[904] | 1141 | int ry = (*it) & ((1 << Y_WIDTH) - 1); |
---|
| 1142 | int rx = (*it >> Y_WIDTH) & ((1 << X_WIDTH) - 1); |
---|
| 1143 | int rt = (*it) >> (X_WIDTH + Y_WIDTH); |
---|
| 1144 | |
---|
| 1145 | if (rt == 0) |
---|
| 1146 | { |
---|
| 1147 | std::cout << "Deactivate CMD router (" << rx << "," << ry << ")" |
---|
| 1148 | << std::endl; |
---|
| 1149 | clusters[rx][ry]->int_router_cmd[0]->set_disable_mask(faulty_mask); |
---|
| 1150 | continue; |
---|
| 1151 | } |
---|
| 1152 | if (rt == 1) |
---|
| 1153 | { |
---|
| 1154 | std::cout << "Deactivate RSP router (" << rx << "," << ry << ")" |
---|
| 1155 | << std::endl; |
---|
| 1156 | clusters[rx][ry]->int_router_rsp[0]->set_disable_mask(faulty_mask); |
---|
| 1157 | continue; |
---|
| 1158 | } |
---|
| 1159 | if (rt == 2) |
---|
| 1160 | { |
---|
| 1161 | std::cout << "Deactivate M2P router (" << rx << "," << ry << ")" |
---|
| 1162 | << std::endl; |
---|
| 1163 | clusters[rx][ry]->int_router_cmd[1]->set_disable_mask(faulty_mask); |
---|
| 1164 | continue; |
---|
| 1165 | } |
---|
| 1166 | if (rt == 3) |
---|
| 1167 | { |
---|
| 1168 | std::cout << "Deactivate P2M router (" << rx << "," << ry << ")" |
---|
| 1169 | << std::endl; |
---|
| 1170 | clusters[rx][ry]->int_router_rsp[1]->set_disable_mask(faulty_mask); |
---|
| 1171 | continue; |
---|
| 1172 | } |
---|
| 1173 | if (rt == 4) |
---|
| 1174 | { |
---|
| 1175 | std::cout << "Deactivate CLACK router (" << rx << "," << ry << ")" |
---|
| 1176 | << std::endl; |
---|
| 1177 | clusters[rx][ry]->int_router_cmd[2]->set_disable_mask(faulty_mask); |
---|
| 1178 | continue; |
---|
| 1179 | } |
---|
[855] | 1180 | } |
---|
| 1181 | |
---|
[747] | 1182 | std::cout << std::endl; |
---|
| 1183 | |
---|
| 1184 | /////////////////////////////////////////////////////////////////////////////// |
---|
| 1185 | // Net-list |
---|
| 1186 | /////////////////////////////////////////////////////////////////////////////// |
---|
| 1187 | |
---|
| 1188 | // IOX network connexion |
---|
| 1189 | iox_network->p_clk (signal_clk); |
---|
| 1190 | iox_network->p_resetn (signal_resetn); |
---|
| 1191 | iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); |
---|
| 1192 | iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev); |
---|
| 1193 | iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); |
---|
| 1194 | iox_network->p_to_ini[IOX_IOPI_INI_ID] (signal_vci_ini_iopi); |
---|
| 1195 | |
---|
| 1196 | iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); |
---|
| 1197 | iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); |
---|
| 1198 | iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); |
---|
| 1199 | iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); |
---|
| 1200 | iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); |
---|
| 1201 | iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); |
---|
| 1202 | iox_network->p_to_tgt[IOX_IOPI_TGT_ID] (signal_vci_tgt_iopi); |
---|
[769] | 1203 | iox_network->p_to_tgt[IOX_SIMH_TGT_ID] (signal_vci_tgt_simh); |
---|
[747] | 1204 | |
---|
| 1205 | if (cluster_iob0 != cluster_iob1) |
---|
| 1206 | { |
---|
| 1207 | iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); |
---|
| 1208 | iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); |
---|
| 1209 | } |
---|
| 1210 | |
---|
| 1211 | // BDEV connexion |
---|
| 1212 | bdev->p_clk (signal_clk); |
---|
| 1213 | bdev->p_resetn (signal_resetn); |
---|
| 1214 | bdev->p_irq (signal_irq_bdev); |
---|
| 1215 | bdev->p_vci_target (signal_vci_tgt_bdev); |
---|
| 1216 | bdev->p_vci_initiator (signal_vci_ini_bdev); |
---|
| 1217 | |
---|
| 1218 | std::cout << " - BDEV connected" << std::endl; |
---|
| 1219 | |
---|
| 1220 | // FBUF connexion |
---|
| 1221 | fbuf->p_clk (signal_clk); |
---|
| 1222 | fbuf->p_resetn (signal_resetn); |
---|
| 1223 | fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
| 1224 | |
---|
| 1225 | std::cout << " - FBUF connected" << std::endl; |
---|
| 1226 | |
---|
| 1227 | // MNIC connexion |
---|
| 1228 | mnic->p_clk (signal_clk); |
---|
| 1229 | mnic->p_resetn (signal_resetn); |
---|
| 1230 | mnic->p_vci (signal_vci_tgt_mnic); |
---|
| 1231 | for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) |
---|
| 1232 | { |
---|
| 1233 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
| 1234 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
| 1235 | } |
---|
| 1236 | |
---|
| 1237 | std::cout << " - MNIC connected" << std::endl; |
---|
| 1238 | |
---|
| 1239 | // MTTY connexion |
---|
| 1240 | mtty->p_clk (signal_clk); |
---|
| 1241 | mtty->p_resetn (signal_resetn); |
---|
| 1242 | mtty->p_vci (signal_vci_tgt_mtty); |
---|
[875] | 1243 | for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) |
---|
| 1244 | { |
---|
| 1245 | mtty->p_irq[i] (signal_irq_mtty_rx[i]); |
---|
| 1246 | } |
---|
[747] | 1247 | std::cout << " - MTTY connected" << std::endl; |
---|
| 1248 | |
---|
| 1249 | // CDMA connexion |
---|
| 1250 | cdma->p_clk (signal_clk); |
---|
| 1251 | cdma->p_resetn (signal_resetn); |
---|
| 1252 | cdma->p_vci_target (signal_vci_tgt_cdma); |
---|
| 1253 | cdma->p_vci_initiator (signal_vci_ini_cdma); |
---|
| 1254 | for ( size_t i=0 ; i<(NB_NIC_CHANNELS*2) ; i++) |
---|
| 1255 | { |
---|
| 1256 | cdma->p_irq[i] (signal_irq_cdma[i]); |
---|
| 1257 | } |
---|
| 1258 | |
---|
| 1259 | std::cout << " - CDMA connected" << std::endl; |
---|
| 1260 | |
---|
| 1261 | // IOPI connexion |
---|
| 1262 | iopi->p_clk (signal_clk); |
---|
| 1263 | iopi->p_resetn (signal_resetn); |
---|
| 1264 | iopi->p_vci_target (signal_vci_tgt_iopi); |
---|
| 1265 | iopi->p_vci_initiator (signal_vci_ini_iopi); |
---|
| 1266 | for ( size_t i=0 ; i<32 ; i++) |
---|
| 1267 | { |
---|
| 1268 | if (i < NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_rx[i]); |
---|
| 1269 | else if(i < 2 ) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1270 | else if(i < 2+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-2]); |
---|
| 1271 | else if(i < 4 ) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1272 | else if(i < 4+NB_CMA_CHANNELS) iopi->p_hwi[i] (signal_irq_cdma[i-4]); |
---|
| 1273 | else if(i < 8) iopi->p_hwi[i] (signal_irq_false); |
---|
[875] | 1274 | else if(i < 9) iopi->p_hwi[i] (signal_irq_bdev); |
---|
| 1275 | else if(i < 16) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1276 | else if(i < 16+NB_TTY_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_rx[i-16]); |
---|
[747] | 1277 | else iopi->p_hwi[i] (signal_irq_false); |
---|
| 1278 | } |
---|
| 1279 | |
---|
| 1280 | std::cout << " - IOPIC connected" << std::endl; |
---|
| 1281 | |
---|
[769] | 1282 | // Simhelper connexion |
---|
| 1283 | simh->p_clk(signal_clk); |
---|
| 1284 | simh->p_resetn(signal_resetn); |
---|
| 1285 | simh->p_vci(signal_vci_tgt_simh); |
---|
[747] | 1286 | |
---|
| 1287 | // IOB0 cluster connexion to IOX network |
---|
| 1288 | (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); |
---|
| 1289 | (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); |
---|
| 1290 | |
---|
| 1291 | // IOB1 cluster connexion to IOX network |
---|
| 1292 | // (only when there is more than 1 cluster) |
---|
| 1293 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 1294 | { |
---|
[806] | 1295 | (*clusters[X_SIZE-1][Y_SIZE-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); |
---|
| 1296 | (*clusters[X_SIZE-1][Y_SIZE-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); |
---|
[747] | 1297 | } |
---|
| 1298 | |
---|
| 1299 | // All clusters Clock & RESET connexions |
---|
[806] | 1300 | for ( size_t x = 0; x < (X_SIZE); x++ ) |
---|
[747] | 1301 | { |
---|
[806] | 1302 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
[747] | 1303 | { |
---|
| 1304 | clusters[x][y]->p_clk (signal_clk); |
---|
| 1305 | clusters[x][y]->p_resetn (signal_resetn); |
---|
| 1306 | } |
---|
| 1307 | } |
---|
| 1308 | |
---|
| 1309 | // Inter Clusters horizontal connections |
---|
[806] | 1310 | if (X_SIZE > 1) |
---|
[747] | 1311 | { |
---|
[806] | 1312 | for (size_t x = 0; x < (X_SIZE-1); x++) |
---|
[747] | 1313 | { |
---|
[806] | 1314 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
[747] | 1315 | { |
---|
| 1316 | for (size_t k = 0; k < 3; k++) |
---|
| 1317 | { |
---|
| 1318 | clusters[x][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1319 | clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1320 | clusters[x][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
| 1321 | clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
| 1322 | } |
---|
| 1323 | |
---|
| 1324 | for (size_t k = 0; k < 2; k++) |
---|
| 1325 | { |
---|
| 1326 | clusters[x][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1327 | clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1328 | clusters[x][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
| 1329 | clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
| 1330 | } |
---|
| 1331 | |
---|
| 1332 | clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1333 | clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1334 | clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1335 | clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1336 | clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1337 | clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1338 | clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1339 | clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1340 | } |
---|
| 1341 | } |
---|
| 1342 | } |
---|
| 1343 | |
---|
| 1344 | std::cout << std::endl << "Horizontal connections established" << std::endl; |
---|
| 1345 | |
---|
| 1346 | // Inter Clusters vertical connections |
---|
[806] | 1347 | if (Y_SIZE > 1) |
---|
[747] | 1348 | { |
---|
[806] | 1349 | for (size_t y = 0; y < (Y_SIZE-1); y++) |
---|
[747] | 1350 | { |
---|
[806] | 1351 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 1352 | { |
---|
| 1353 | for (size_t k = 0; k < 3; k++) |
---|
| 1354 | { |
---|
| 1355 | clusters[x][y]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1356 | clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1357 | clusters[x][y]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
| 1358 | clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
| 1359 | } |
---|
| 1360 | |
---|
| 1361 | for (size_t k = 0; k < 2; k++) |
---|
| 1362 | { |
---|
| 1363 | clusters[x][y]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1364 | clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1365 | clusters[x][y]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
| 1366 | clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
| 1367 | } |
---|
| 1368 | |
---|
| 1369 | clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1370 | clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1371 | clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1372 | clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1373 | clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1374 | clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1375 | clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1376 | clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1377 | } |
---|
| 1378 | } |
---|
| 1379 | } |
---|
| 1380 | |
---|
| 1381 | std::cout << "Vertical connections established" << std::endl; |
---|
| 1382 | |
---|
| 1383 | // East & West boundary cluster connections |
---|
[806] | 1384 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
[747] | 1385 | { |
---|
| 1386 | for (size_t k = 0; k < 3; k++) |
---|
| 1387 | { |
---|
[751] | 1388 | clusters[0][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_false_int_cmd_in[0][y][WEST][k]); |
---|
| 1389 | clusters[0][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_false_int_cmd_out[0][y][WEST][k]); |
---|
[806] | 1390 | clusters[X_SIZE-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[X_SIZE-1][y][EAST][k]); |
---|
| 1391 | clusters[X_SIZE-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[X_SIZE-1][y][EAST][k]); |
---|
[747] | 1392 | } |
---|
| 1393 | |
---|
| 1394 | for (size_t k = 0; k < 2; k++) |
---|
| 1395 | { |
---|
[751] | 1396 | clusters[0][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_false_int_rsp_in[0][y][WEST][k]); |
---|
| 1397 | clusters[0][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_false_int_rsp_out[0][y][WEST][k]); |
---|
[806] | 1398 | clusters[X_SIZE-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[X_SIZE-1][y][EAST][k]); |
---|
| 1399 | clusters[X_SIZE-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[X_SIZE-1][y][EAST][k]); |
---|
[747] | 1400 | } |
---|
| 1401 | |
---|
[751] | 1402 | clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); |
---|
| 1403 | clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); |
---|
| 1404 | clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); |
---|
| 1405 | clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); |
---|
[747] | 1406 | |
---|
[806] | 1407 | clusters[X_SIZE-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[X_SIZE-1][y][EAST]); |
---|
| 1408 | clusters[X_SIZE-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[X_SIZE-1][y][EAST]); |
---|
| 1409 | clusters[X_SIZE-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[X_SIZE-1][y][EAST]); |
---|
| 1410 | clusters[X_SIZE-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[X_SIZE-1][y][EAST]); |
---|
[747] | 1411 | } |
---|
| 1412 | |
---|
| 1413 | std::cout << "East & West boundaries established" << std::endl; |
---|
| 1414 | |
---|
| 1415 | // North & South boundary clusters connections |
---|
[806] | 1416 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 1417 | { |
---|
| 1418 | for (size_t k = 0; k < 3; k++) |
---|
| 1419 | { |
---|
[751] | 1420 | clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); |
---|
| 1421 | clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); |
---|
[806] | 1422 | clusters[x][Y_SIZE-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][Y_SIZE-1][NORTH][k]); |
---|
| 1423 | clusters[x][Y_SIZE-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][Y_SIZE-1][NORTH][k]); |
---|
[747] | 1424 | } |
---|
| 1425 | |
---|
| 1426 | for (size_t k = 0; k < 2; k++) |
---|
| 1427 | { |
---|
[751] | 1428 | clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); |
---|
| 1429 | clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); |
---|
[806] | 1430 | clusters[x][Y_SIZE-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][Y_SIZE-1][NORTH][k]); |
---|
| 1431 | clusters[x][Y_SIZE-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][Y_SIZE-1][NORTH][k]); |
---|
[747] | 1432 | } |
---|
| 1433 | |
---|
[751] | 1434 | clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); |
---|
| 1435 | clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); |
---|
| 1436 | clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); |
---|
| 1437 | clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); |
---|
[747] | 1438 | |
---|
[806] | 1439 | clusters[x][Y_SIZE-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][Y_SIZE-1][NORTH]); |
---|
| 1440 | clusters[x][Y_SIZE-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][Y_SIZE-1][NORTH]); |
---|
| 1441 | clusters[x][Y_SIZE-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][Y_SIZE-1][NORTH]); |
---|
| 1442 | clusters[x][Y_SIZE-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][Y_SIZE-1][NORTH]); |
---|
[747] | 1443 | } |
---|
| 1444 | |
---|
| 1445 | std::cout << "North & South boundaries established" << std::endl << std::endl; |
---|
| 1446 | |
---|
| 1447 | //////////////////////////////////////////////////////// |
---|
| 1448 | // Simulation |
---|
| 1449 | /////////////////////////////////////////////////////// |
---|
| 1450 | |
---|
| 1451 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
| 1452 | |
---|
| 1453 | signal_resetn = false; |
---|
| 1454 | signal_irq_false = false; |
---|
| 1455 | |
---|
[751] | 1456 | // network boundaries signals |
---|
[806] | 1457 | for (size_t x = 0; x < X_SIZE ; x++) |
---|
[751] | 1458 | { |
---|
[806] | 1459 | for (size_t y = 0; y < Y_SIZE ; y++) |
---|
[751] | 1460 | { |
---|
| 1461 | for (size_t a = 0; a < 4; a++) |
---|
| 1462 | { |
---|
| 1463 | for (size_t k = 0; k < 3; k++) |
---|
| 1464 | { |
---|
| 1465 | signal_dspin_false_int_cmd_in[x][y][a][k].write = false; |
---|
| 1466 | signal_dspin_false_int_cmd_in[x][y][a][k].read = true; |
---|
| 1467 | signal_dspin_false_int_cmd_out[x][y][a][k].write = false; |
---|
| 1468 | signal_dspin_false_int_cmd_out[x][y][a][k].read = true; |
---|
| 1469 | } |
---|
[750] | 1470 | |
---|
[751] | 1471 | for (size_t k = 0; k < 2; k++) |
---|
| 1472 | { |
---|
| 1473 | signal_dspin_false_int_rsp_in[x][y][a][k].write = false; |
---|
| 1474 | signal_dspin_false_int_rsp_in[x][y][a][k].read = true; |
---|
| 1475 | signal_dspin_false_int_rsp_out[x][y][a][k].write = false; |
---|
| 1476 | signal_dspin_false_int_rsp_out[x][y][a][k].read = true; |
---|
| 1477 | } |
---|
| 1478 | |
---|
| 1479 | signal_dspin_false_ram_cmd_in[x][y][a].write = false; |
---|
| 1480 | signal_dspin_false_ram_cmd_in[x][y][a].read = true; |
---|
| 1481 | signal_dspin_false_ram_cmd_out[x][y][a].write = false; |
---|
| 1482 | signal_dspin_false_ram_cmd_out[x][y][a].read = true; |
---|
| 1483 | |
---|
| 1484 | signal_dspin_false_ram_rsp_in[x][y][a].write = false; |
---|
| 1485 | signal_dspin_false_ram_rsp_in[x][y][a].read = true; |
---|
| 1486 | signal_dspin_false_ram_rsp_out[x][y][a].write = false; |
---|
| 1487 | signal_dspin_false_ram_rsp_out[x][y][a].read = true; |
---|
| 1488 | } |
---|
| 1489 | } |
---|
| 1490 | } |
---|
| 1491 | |
---|
[750] | 1492 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 1493 | signal_resetn = true; |
---|
| 1494 | |
---|
| 1495 | // simulation loop |
---|
[855] | 1496 | struct timeval t1, t2; |
---|
[750] | 1497 | |
---|
[766] | 1498 | // cycles between stats |
---|
[906] | 1499 | const size_t stats_period = 150000; |
---|
[766] | 1500 | const size_t simul_period = debug_ok ? debug_period : stats_period; |
---|
[747] | 1501 | |
---|
[766] | 1502 | for (size_t n = 0; n < ncycles; n += simul_period) |
---|
[750] | 1503 | { |
---|
| 1504 | // stats display |
---|
[766] | 1505 | if((n % stats_period) == 0) |
---|
[750] | 1506 | { |
---|
[766] | 1507 | if (n > 0) |
---|
| 1508 | { |
---|
| 1509 | gettimeofday(&t2, NULL); |
---|
[747] | 1510 | |
---|
[766] | 1511 | uint64_t ms1 = (uint64_t) t1.tv_sec * 1000ULL + |
---|
| 1512 | (uint64_t) t1.tv_usec / 1000; |
---|
| 1513 | uint64_t ms2 = (uint64_t) t2.tv_sec * 1000ULL + |
---|
| 1514 | (uint64_t) t2.tv_usec / 1000; |
---|
[904] | 1515 | std::cerr << "### cycle = " << std::dec << n << " / frequency (Khz) = " |
---|
[766] | 1516 | << (double) stats_period / (double) (ms2 - ms1) << std::endl; |
---|
| 1517 | } |
---|
[747] | 1518 | |
---|
[750] | 1519 | gettimeofday(&t1, NULL); |
---|
| 1520 | } |
---|
[747] | 1521 | |
---|
[750] | 1522 | // Monitor a specific address for one L1 cache |
---|
| 1523 | // clusters[1][1]->proc[0]->cache_monitor(0x50090ULL); |
---|
[747] | 1524 | |
---|
[750] | 1525 | // Monitor a specific address for one L2 cache |
---|
| 1526 | // clusters[0][0]->memc->cache_monitor( 0x170000ULL); |
---|
[747] | 1527 | |
---|
[750] | 1528 | // Monitor a specific address for one XRAM |
---|
| 1529 | // if (n == 3000000) clusters[0][0]->xram->start_monitor( 0x170000ULL , 64); |
---|
[747] | 1530 | |
---|
[750] | 1531 | if (debug_ok and (n > debug_from) and (n % debug_period == 0)) |
---|
| 1532 | { |
---|
| 1533 | std::cout << "****************** cycle " << std::dec << n ; |
---|
| 1534 | std::cout << " ************************************************" << std::endl; |
---|
[747] | 1535 | |
---|
[887] | 1536 | #if 0 |
---|
| 1537 | for (int x = 0; x < X_SIZE; ++x) |
---|
| 1538 | { |
---|
| 1539 | for (int y = 0; y < Y_SIZE; ++y) |
---|
| 1540 | { |
---|
| 1541 | clusters[x][y]->int_router_cmd[0]->print_trace(); |
---|
| 1542 | clusters[x][y]->int_router_rsp[0]->print_trace(); |
---|
| 1543 | } |
---|
| 1544 | } |
---|
| 1545 | #endif |
---|
| 1546 | |
---|
[750] | 1547 | // trace proc[debug_proc_id] |
---|
| 1548 | if ( debug_proc_id != 0xFFFFFFFF ) |
---|
| 1549 | { |
---|
[855] | 1550 | size_t l = debug_proc_id & ((1 << P_WIDTH) - 1); |
---|
| 1551 | size_t cluster_xy = debug_proc_id >> P_WIDTH ; |
---|
| 1552 | size_t x = cluster_xy >> Y_WIDTH; |
---|
| 1553 | size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); |
---|
[747] | 1554 | |
---|
[750] | 1555 | clusters[x][y]->proc[l]->print_trace(1); |
---|
| 1556 | std::ostringstream proc_signame; |
---|
| 1557 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
| 1558 | clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); |
---|
[747] | 1559 | |
---|
[750] | 1560 | clusters[x][y]->xicu->print_trace(l); |
---|
| 1561 | std::ostringstream xicu_signame; |
---|
| 1562 | xicu_signame << "[SIG]XICU_" << x << "_" << y; |
---|
| 1563 | clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); |
---|
[747] | 1564 | |
---|
[750] | 1565 | // clusters[x][y]->mdma->print_trace(); |
---|
| 1566 | // std::ostringstream mdma_signame; |
---|
| 1567 | // mdma_signame << "[SIG]MDMA_" << x << "_" << y; |
---|
| 1568 | // clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_signame.str()); |
---|
[748] | 1569 | |
---|
[750] | 1570 | if( clusters[x][y]->signal_proc_it[l].read() ) |
---|
| 1571 | std::cout << "### IRQ_PROC_" << std::dec |
---|
| 1572 | << x << "_" << y << "_" << l << " ACTIVE" << std::endl; |
---|
| 1573 | } |
---|
[747] | 1574 | |
---|
[750] | 1575 | // trace memc[debug_memc_id] |
---|
| 1576 | if ( debug_memc_id != 0xFFFFFFFF ) |
---|
| 1577 | { |
---|
[855] | 1578 | size_t x = debug_memc_id >> Y_WIDTH; |
---|
| 1579 | size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); |
---|
[747] | 1580 | |
---|
[750] | 1581 | clusters[x][y]->memc->print_trace(0); |
---|
| 1582 | std::ostringstream smemc_tgt; |
---|
| 1583 | smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; |
---|
| 1584 | clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); |
---|
| 1585 | std::ostringstream smemc_ini; |
---|
| 1586 | smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; |
---|
| 1587 | clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); |
---|
[747] | 1588 | |
---|
[750] | 1589 | clusters[x][y]->xram->print_trace(); |
---|
| 1590 | std::ostringstream sxram_tgt; |
---|
| 1591 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
| 1592 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
| 1593 | } |
---|
[747] | 1594 | |
---|
| 1595 | |
---|
[750] | 1596 | // trace XRAM and XRAM network routers in cluster[debug_xram_id] |
---|
| 1597 | if ( debug_xram_id != 0xFFFFFFFF ) |
---|
| 1598 | { |
---|
[855] | 1599 | size_t x = debug_xram_id >> Y_WIDTH; |
---|
| 1600 | size_t y = debug_xram_id & ((1 << Y_WIDTH) - 1); |
---|
[747] | 1601 | |
---|
[750] | 1602 | clusters[x][y]->xram->print_trace(); |
---|
| 1603 | std::ostringstream sxram_tgt; |
---|
| 1604 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
| 1605 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
[747] | 1606 | |
---|
[750] | 1607 | clusters[x][y]->ram_router_cmd->print_trace(); |
---|
| 1608 | clusters[x][y]->ram_router_rsp->print_trace(); |
---|
| 1609 | } |
---|
[747] | 1610 | |
---|
[750] | 1611 | // trace iob, iox and external peripherals |
---|
| 1612 | if ( debug_iob ) |
---|
| 1613 | { |
---|
| 1614 | clusters[0][0]->iob->print_trace(); |
---|
[806] | 1615 | clusters[X_SIZE-1][Y_SIZE-1]->iob->print_trace(); |
---|
[750] | 1616 | // clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); |
---|
| 1617 | // clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); |
---|
| 1618 | // clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); |
---|
[747] | 1619 | |
---|
[750] | 1620 | signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); |
---|
| 1621 | signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); |
---|
[747] | 1622 | |
---|
[750] | 1623 | // cdma->print_trace(); |
---|
| 1624 | // signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT"); |
---|
| 1625 | // signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI"); |
---|
[747] | 1626 | |
---|
[750] | 1627 | // mtty->print_trace(); |
---|
| 1628 | // signal_vci_tgt_mtty.print_trace("[SIG]IOX_MTTY_TGT"); |
---|
[747] | 1629 | |
---|
[750] | 1630 | bdev->print_trace(); |
---|
| 1631 | signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); |
---|
| 1632 | signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); |
---|
[747] | 1633 | |
---|
[750] | 1634 | mnic->print_trace(); |
---|
| 1635 | signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); |
---|
[747] | 1636 | |
---|
[750] | 1637 | // fbuf->print_trace(); |
---|
| 1638 | // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF"); |
---|
[747] | 1639 | |
---|
[750] | 1640 | iopi->print_trace(); |
---|
| 1641 | signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); |
---|
| 1642 | signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); |
---|
[769] | 1643 | |
---|
| 1644 | signal_vci_tgt_simh.print_trace("[SIG]SIMH_TGT"); |
---|
| 1645 | |
---|
[750] | 1646 | iox_network->print_trace(); |
---|
[747] | 1647 | |
---|
[750] | 1648 | // interrupts |
---|
| 1649 | if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVE" << std::endl; |
---|
[875] | 1650 | if (signal_irq_mtty_rx[0]) std::cout << "### IRQ_MTTY ACTIVE" << std::endl; |
---|
[750] | 1651 | if (signal_irq_mnic_rx[0]) std::cout << "### IRQ_MNIC_RX[0] ACTIVE" << std::endl; |
---|
| 1652 | if (signal_irq_mnic_rx[1]) std::cout << "### IRQ_MNIC_RX[1] ACTIVE" << std::endl; |
---|
| 1653 | if (signal_irq_mnic_tx[0]) std::cout << "### IRQ_MNIC_TX[0] ACTIVE" << std::endl; |
---|
| 1654 | if (signal_irq_mnic_tx[1]) std::cout << "### IRQ_MNIC_TX[1] ACTIVE" << std::endl; |
---|
| 1655 | } |
---|
| 1656 | } |
---|
[747] | 1657 | |
---|
[766] | 1658 | sc_start(sc_core::sc_time(simul_period, SC_NS)); |
---|
[750] | 1659 | } |
---|
| 1660 | return EXIT_SUCCESS; |
---|
[747] | 1661 | } |
---|
| 1662 | |
---|
| 1663 | int sc_main (int argc, char *argv[]) |
---|
| 1664 | { |
---|
| 1665 | try { |
---|
| 1666 | return _main(argc, argv); |
---|
[769] | 1667 | } catch (soclib::exception::RunTimeError &e) { |
---|
| 1668 | std::cout << "RunTimeError: " << e.what() << std::endl; |
---|
[747] | 1669 | } catch (std::exception &e) { |
---|
| 1670 | std::cout << e.what() << std::endl; |
---|
| 1671 | } catch (...) { |
---|
| 1672 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 1673 | throw; |
---|
| 1674 | } |
---|
| 1675 | return 1; |
---|
| 1676 | } |
---|
| 1677 | |
---|
| 1678 | |
---|
| 1679 | // Local Variables: |
---|
| 1680 | // tab-width: 3 |
---|
| 1681 | // c-basic-offset: 3 |
---|
| 1682 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 1683 | // indent-tabs-mode: nil |
---|
| 1684 | // End: |
---|
| 1685 | |
---|
| 1686 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|