[747] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.cpp |
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[806] | 3 | // Author: Alain Greiner |
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[747] | 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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[806] | 8 | // Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components. |
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[747] | 9 | // These two clusters contain 6 extra components: |
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| 10 | // - 1 vci_io_bridge (connected to the 3 networks. |
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| 11 | // - 3 vci_dspin_wrapper for the IOB. |
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[806] | 12 | // - 2 dspin_local_crossbar for commands and responses. |
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[747] | 13 | ////////////////////////////////////////////////////////////////////////////// |
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| 14 | |
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| 15 | #include "../include/tsar_iob_cluster.h" |
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| 16 | |
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| 17 | #define tmpl(x) \ |
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| 18 | template<typename vci_param_int , typename vci_param_ext,\ |
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| 19 | size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\ |
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| 20 | size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\ |
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| 21 | x TsarIobCluster<\ |
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| 22 | vci_param_int , vci_param_ext,\ |
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| 23 | dspin_int_cmd_width, dspin_int_rsp_width,\ |
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| 24 | dspin_ram_cmd_width, dspin_ram_rsp_width> |
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| 25 | |
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| 26 | namespace soclib { namespace caba { |
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| 27 | |
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| 28 | ////////////////////////////////////////////////////////////////////////// |
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| 29 | // Constructor |
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| 30 | ////////////////////////////////////////////////////////////////////////// |
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| 31 | tmpl(/**/)::TsarIobCluster( |
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[806] | 32 | sc_module_name insname, |
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| 33 | size_t nb_procs, |
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| 34 | size_t nb_dmas, |
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| 35 | size_t x_id, |
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| 36 | size_t y_id, |
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| 37 | size_t x_size, |
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| 38 | size_t y_size, |
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[747] | 39 | |
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[806] | 40 | size_t p_width, |
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[747] | 41 | |
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[806] | 42 | const soclib::common::MappingTable &mt_int, |
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| 43 | const soclib::common::MappingTable &mt_ram, |
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| 44 | const soclib::common::MappingTable &mt_iox, |
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[747] | 45 | |
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[806] | 46 | size_t x_width, |
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| 47 | size_t y_width, |
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| 48 | size_t l_width, |
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[747] | 49 | |
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[806] | 50 | size_t int_memc_tgt_id, // local index |
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| 51 | size_t int_xicu_tgt_id, // local index |
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| 52 | size_t int_mdma_tgt_id, // local index |
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[926] | 53 | size_t int_drom_tgt_id, // local index |
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[806] | 54 | size_t int_iobx_tgt_id, // local index |
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[747] | 55 | |
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[806] | 56 | size_t int_proc_ini_id, // local index |
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| 57 | size_t int_mdma_ini_id, // local index |
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| 58 | size_t int_iobx_ini_id, // local index |
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[747] | 59 | |
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[806] | 60 | size_t ram_xram_tgt_id, // local index |
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| 61 | size_t ram_memc_ini_id, // local index |
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| 62 | size_t ram_iobx_ini_id, // local index |
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[747] | 63 | |
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[806] | 64 | bool is_io, // is IO cluster (IOB)? |
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| 65 | size_t iox_iobx_tgt_id, // local_index |
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| 66 | size_t iox_iobx_ini_id, // local index |
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[747] | 67 | |
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[806] | 68 | size_t memc_ways, |
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| 69 | size_t memc_sets, |
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| 70 | size_t l1_i_ways, |
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| 71 | size_t l1_i_sets, |
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| 72 | size_t l1_d_ways, |
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| 73 | size_t l1_d_sets, |
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| 74 | size_t xram_latency, |
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[961] | 75 | size_t xcu_nb_hwi, |
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| 76 | size_t xcu_nb_pti, |
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| 77 | size_t xcu_nb_wti, |
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| 78 | size_t xcu_nb_out, |
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[963] | 79 | size_t irq_per_proc, |
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[747] | 80 | |
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[1015] | 81 | bool disable_procs, |
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[748] | 82 | |
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[806] | 83 | const Loader &loader, |
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| 84 | |
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| 85 | uint32_t frozen_cycles, |
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| 86 | uint32_t debug_start_cycle, |
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| 87 | bool memc_debug_ok, |
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| 88 | bool proc_debug_ok, |
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| 89 | bool iob_debug_ok ) : |
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| 90 | |
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| 91 | // constructor initialization list |
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| 92 | |
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| 93 | soclib::caba::BaseModule(insname), |
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| 94 | p_clk("clk"), |
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[1001] | 95 | p_resetn("resetn"), |
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[1015] | 96 | p_false("false"), |
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| 97 | m_nb_procs(nb_procs), |
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| 98 | m_disable_procs(disable_procs) |
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[747] | 99 | { |
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| 100 | |
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[806] | 101 | assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates"); |
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[747] | 102 | |
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[1000] | 103 | size_t cluster_id = (x_id << y_width) | y_id; |
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[806] | 104 | |
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[747] | 105 | // Vectors of DSPIN ports for inter-cluster communications |
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| 106 | p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); |
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| 107 | p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3); |
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| 108 | p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2); |
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| 109 | p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2); |
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| 110 | |
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| 111 | p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); |
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| 112 | p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); |
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| 113 | p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); |
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| 114 | p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); |
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| 115 | |
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| 116 | // VCI ports from IOB to IOX network (only in IO clusters) |
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[806] | 117 | if (is_io) |
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[747] | 118 | { |
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| 119 | p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; |
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[806] | 120 | p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; |
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[747] | 121 | } |
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| 122 | |
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| 123 | ///////////////////////////////////////////////////////////////////////////// |
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| 124 | // Hardware components |
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| 125 | ///////////////////////////////////////////////////////////////////////////// |
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| 126 | |
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| 127 | //////////// PROCS |
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[1015] | 128 | for (size_t p = 0; p < nb_procs && !m_disable_procs; p++) |
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[806] | 129 | { |
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[747] | 130 | std::ostringstream s_proc; |
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| 131 | s_proc << "proc_" << x_id << "_" << y_id << "_" << p; |
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| 132 | proc[p] = new VciCcVCacheWrapper<vci_param_int, |
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| 133 | dspin_int_cmd_width, |
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| 134 | dspin_int_rsp_width, |
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| 135 | GdbServer<Mips32ElIss> >( |
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| 136 | s_proc.str().c_str(), |
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[806] | 137 | (cluster_id << p_width) | p, // GLOBAL PROC_ID |
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[747] | 138 | mt_int, // Mapping Table INT network |
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| 139 | IntTab(cluster_id,p), // SRCID |
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[806] | 140 | (cluster_id << l_width) | p, // CC_GLOBAL_ID |
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[747] | 141 | 8, // ITLB ways |
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| 142 | 8, // ITLB sets |
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| 143 | 8, // DTLB ways |
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| 144 | 8, // DTLB sets |
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| 145 | l1_i_ways, l1_i_sets, 16, // ICACHE size |
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| 146 | l1_d_ways, l1_d_sets, 16, // DCACHE size |
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| 147 | 4, // WBUF nlines |
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| 148 | 4, // WBUF nwords |
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[806] | 149 | x_width, // number of bits for x coordinate |
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| 150 | y_width, // number of bits for y coordinate |
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[747] | 151 | frozen_cycles, // max frozen cycles |
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| 152 | debug_start_cycle, |
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| 153 | proc_debug_ok); |
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[748] | 154 | |
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| 155 | // initialize physical address extension with cluster ID when using |
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| 156 | // distributed boot |
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[1027] | 157 | proc[p]->set_dcache_paddr_ext_reset(cluster_id); |
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| 158 | proc[p]->set_icache_paddr_ext_reset(cluster_id); |
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[747] | 159 | } |
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| 160 | |
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[806] | 161 | /////////// MEMC |
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[747] | 162 | std::ostringstream s_memc; |
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| 163 | s_memc << "memc_" << x_id << "_" << y_id; |
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| 164 | memc = new VciMemCache<vci_param_int, |
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| 165 | vci_param_ext, |
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| 166 | dspin_int_rsp_width, |
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| 167 | dspin_int_cmd_width>( |
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| 168 | s_memc.str().c_str(), |
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| 169 | mt_int, // Mapping Table INT network |
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| 170 | mt_ram, // Mapping Table RAM network |
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| 171 | IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network |
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| 172 | IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network |
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| 173 | x_width, // number of bits for x coordinate |
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| 174 | y_width, // number of bits for y coordinate |
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| 175 | memc_ways, memc_sets, 16, // CACHE SIZE |
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| 176 | 3, // MAX NUMBER OF COPIES |
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| 177 | 4096, // HEAP SIZE |
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| 178 | 8, // TRANSACTION TABLE DEPTH |
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| 179 | 8, // UPDATE TABLE DEPTH |
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| 180 | 8, // INVALIDATE TABLE DEPTH |
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| 181 | debug_start_cycle, |
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| 182 | memc_debug_ok ); |
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| 183 | |
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| 184 | std::ostringstream s_wi_memc; |
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| 185 | s_wi_memc << "memc_wi_" << x_id << "_" << y_id; |
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| 186 | memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 187 | dspin_ram_cmd_width, |
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| 188 | dspin_ram_rsp_width>( |
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| 189 | s_wi_memc.str().c_str(), |
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| 190 | x_width + y_width + l_width); |
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| 191 | |
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| 192 | /////////// XICU |
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| 193 | std::ostringstream s_xicu; |
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| 194 | s_xicu << "xicu_" << x_id << "_" << y_id; |
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| 195 | xicu = new VciXicu<vci_param_int>( |
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| 196 | s_xicu.str().c_str(), |
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| 197 | mt_int, // mapping table INT network |
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| 198 | IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space |
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[961] | 199 | xcu_nb_pti, // number of timer IRQs |
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| 200 | xcu_nb_hwi, // number of hard IRQs |
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| 201 | xcu_nb_wti, // number of soft IRQs |
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| 202 | xcu_nb_out, // number of output IRQs |
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[1001] | 203 | 6); // number of config regs |
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[747] | 204 | |
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| 205 | //////////// MDMA |
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| 206 | std::ostringstream s_mdma; |
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| 207 | s_mdma << "mdma_" << x_id << "_" << y_id; |
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| 208 | mdma = new VciMultiDma<vci_param_int>( |
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| 209 | s_mdma.str().c_str(), |
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| 210 | mt_int, |
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| 211 | IntTab(cluster_id, nb_procs), // SRCID |
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| 212 | IntTab(cluster_id, int_mdma_tgt_id), // TGTID |
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| 213 | 64, // burst size |
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| 214 | nb_dmas); // number of IRQs |
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| 215 | |
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[926] | 216 | /////////// DISTRIBUTED ROM |
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| 217 | std::ostringstream s_drom; |
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| 218 | s_drom << "drom_" << x_id << "_" << y_id; |
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| 219 | drom = new VciSimpleRom<vci_param_int>( |
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| 220 | s_drom.str().c_str(), |
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| 221 | IntTab(cluster_id, int_drom_tgt_id), |
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[748] | 222 | mt_int, |
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| 223 | loader, |
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| 224 | x_width + y_width); // msb drop bits |
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| 225 | |
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[747] | 226 | /////////// Direct LOCAL_XBAR(S) |
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| 227 | size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1; |
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[748] | 228 | size_t nb_direct_targets = is_io ? 5 : 4; |
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[747] | 229 | |
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| 230 | std::ostringstream s_int_xbar_d; |
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| 231 | s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; |
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| 232 | int_xbar_d = new VciLocalCrossbar<vci_param_int>( |
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| 233 | s_int_xbar_d.str().c_str(), |
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| 234 | mt_int, // mapping table |
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| 235 | cluster_id, // cluster id |
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| 236 | nb_direct_initiators, // number of local initiators |
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[806] | 237 | nb_direct_targets, // number of local targets |
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[1001] | 238 | 0, // default target |
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| 239 | true ); // hardware barrier |
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[747] | 240 | |
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| 241 | std::ostringstream s_int_dspin_ini_wrapper_gate_d; |
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| 242 | s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_" |
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| 243 | << x_id << "_" << y_id; |
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| 244 | int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int, |
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| 245 | dspin_int_cmd_width, |
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| 246 | dspin_int_rsp_width>( |
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| 247 | s_int_dspin_ini_wrapper_gate_d.str().c_str(), |
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| 248 | x_width + y_width + l_width); |
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| 249 | |
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| 250 | std::ostringstream s_int_dspin_tgt_wrapper_gate_d; |
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| 251 | s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_" |
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| 252 | << x_id << "_" << y_id; |
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| 253 | int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int, |
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| 254 | dspin_int_cmd_width, |
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| 255 | dspin_int_rsp_width>( |
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| 256 | s_int_dspin_tgt_wrapper_gate_d.str().c_str(), |
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| 257 | x_width + y_width + l_width); |
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| 258 | |
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| 259 | //////////// Coherence LOCAL_XBAR(S) |
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| 260 | std::ostringstream s_int_xbar_m2p_c; |
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| 261 | s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; |
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| 262 | int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 263 | s_int_xbar_m2p_c.str().c_str(), |
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| 264 | mt_int, // mapping table |
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| 265 | x_id, y_id, // cluster coordinates |
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| 266 | x_width, y_width, l_width, // several dests |
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| 267 | 1, // number of local sources |
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[806] | 268 | nb_procs, // number of local dests |
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| 269 | 2, 2, // fifo depths |
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[747] | 270 | true, // pseudo CMD |
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| 271 | false, // no routing table |
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[1001] | 272 | true, // broacast |
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| 273 | true ); // hardware barrier |
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[747] | 274 | |
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| 275 | std::ostringstream s_int_xbar_p2m_c; |
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| 276 | s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; |
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| 277 | int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 278 | s_int_xbar_p2m_c.str().c_str(), |
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| 279 | mt_int, // mapping table |
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| 280 | x_id, y_id, // cluster coordinates |
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| 281 | x_width, y_width, 0, // only one dest |
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| 282 | nb_procs, // number of local sources |
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| 283 | 1, // number of local dests |
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[806] | 284 | 2, 2, // fifo depths |
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[747] | 285 | false, // pseudo RSP |
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| 286 | false, // no routing table |
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[1001] | 287 | false, // no broacast |
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| 288 | true ); // hardware barrier |
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[747] | 289 | |
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| 290 | std::ostringstream s_int_xbar_clack_c; |
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| 291 | s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; |
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| 292 | int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 293 | s_int_xbar_clack_c.str().c_str(), |
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| 294 | mt_int, // mapping table |
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| 295 | x_id, y_id, // cluster coordinates |
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| 296 | x_width, y_width, l_width, |
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| 297 | 1, // number of local sources |
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[806] | 298 | nb_procs, // number of local targets |
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[747] | 299 | 1, 1, // fifo depths |
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| 300 | true, // CMD |
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| 301 | false, // no routing table |
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[1001] | 302 | false, // broadcast |
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| 303 | true ); // hardware barrier |
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[747] | 304 | |
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[995] | 305 | const bool ROUTER_CONFIG_SUPPORTED = true; |
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| 306 | |
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[747] | 307 | ////////////// INT ROUTER(S) |
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[851] | 308 | int_router_cmd = new DspinRouter<dspin_int_cmd_width>*[3]; |
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| 309 | for (int k = 0; k < 3; k++) |
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| 310 | { |
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| 311 | std::ostringstream s_int_router_cmd; |
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| 312 | s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id << "_" << k; |
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| 313 | int_router_cmd[k] = new DspinRouter<dspin_int_cmd_width>( |
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| 314 | s_int_router_cmd.str().c_str(), |
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| 315 | x_id, y_id, |
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| 316 | x_width, y_width, |
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| 317 | 4, 4, |
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[995] | 318 | (k == 1), |
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| 319 | ROUTER_CONFIG_SUPPORTED); |
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[851] | 320 | } |
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[747] | 321 | |
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[851] | 322 | int_router_rsp = new DspinRouter<dspin_int_rsp_width>*[2]; |
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| 323 | for (int k = 0; k < 2; k++) |
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| 324 | { |
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| 325 | std::ostringstream s_int_router_rsp; |
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| 326 | s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id << "_" << k; |
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| 327 | int_router_rsp[k] = new DspinRouter<dspin_int_rsp_width>( |
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| 328 | s_int_router_rsp.str().c_str(), |
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| 329 | x_id, y_id, |
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| 330 | x_width, y_width, |
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| 331 | 4, 4, |
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[995] | 332 | false, |
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| 333 | ROUTER_CONFIG_SUPPORTED); |
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[851] | 334 | } |
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[747] | 335 | |
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| 336 | ////////////// XRAM |
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| 337 | std::ostringstream s_xram; |
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| 338 | s_xram << "xram_" << x_id << "_" << y_id; |
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| 339 | xram = new VciSimpleRam<vci_param_ext>( |
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| 340 | s_xram.str().c_str(), |
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| 341 | IntTab(cluster_id, ram_xram_tgt_id), |
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| 342 | mt_ram, |
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| 343 | loader, |
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| 344 | xram_latency); |
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| 345 | |
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| 346 | std::ostringstream s_wt_xram; |
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| 347 | s_wt_xram << "xram_wt_" << x_id << "_" << y_id; |
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| 348 | xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext, |
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| 349 | dspin_ram_cmd_width, |
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| 350 | dspin_ram_rsp_width>( |
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| 351 | s_wt_xram.str().c_str(), |
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| 352 | x_width + y_width + l_width); |
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| 353 | |
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| 354 | ///////////// RAM ROUTER(S) |
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| 355 | std::ostringstream s_ram_router_cmd; |
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| 356 | s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; |
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| 357 | ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>( |
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| 358 | s_ram_router_cmd.str().c_str(), |
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| 359 | x_id, y_id, // router coordinates in mesh |
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| 360 | x_width, // x field width in first flit |
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| 361 | y_width, // y field width in first flit |
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| 362 | 4, 4); // input & output fifo depths |
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| 363 | |
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| 364 | std::ostringstream s_ram_router_rsp; |
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| 365 | s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; |
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| 366 | ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>( |
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| 367 | s_ram_router_rsp.str().c_str(), |
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| 368 | x_id, y_id, // coordinates in mesh |
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| 369 | x_width, // x field width in first flit |
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| 370 | y_width, // y field width in first flit |
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| 371 | 4, 4); // input & output fifo depths |
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| 372 | |
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| 373 | |
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| 374 | ////////////////////// I/O CLUSTER ONLY /////////////////////// |
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| 375 | if ( is_io ) |
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| 376 | { |
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| 377 | /////////// IO_BRIDGE |
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| 378 | std::ostringstream s_iob; |
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[806] | 379 | s_iob << "iob_" << x_id << "_" << y_id; |
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[747] | 380 | iob = new VciIoBridge<vci_param_int, |
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[806] | 381 | vci_param_ext>( |
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[747] | 382 | s_iob.str().c_str(), |
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| 383 | mt_ram, // EXT network maptab |
---|
| 384 | mt_int, // INT network maptab |
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| 385 | mt_iox, // IOX network maptab |
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| 386 | IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID |
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| 387 | IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID |
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| 388 | IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID |
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| 389 | IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID |
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| 390 | 16, // cache line words |
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| 391 | 8, // IOTLB ways |
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| 392 | 8, // IOTLB sets |
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| 393 | debug_start_cycle, |
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| 394 | iob_debug_ok ); |
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[806] | 395 | |
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[747] | 396 | std::ostringstream s_iob_ram_wi; |
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[806] | 397 | s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; |
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[747] | 398 | iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 399 | dspin_ram_cmd_width, |
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| 400 | dspin_ram_rsp_width>( |
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| 401 | s_iob_ram_wi.str().c_str(), |
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| 402 | vci_param_int::S); |
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| 403 | |
---|
| 404 | std::ostringstream s_ram_xbar_cmd; |
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| 405 | s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id; |
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| 406 | ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>( |
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| 407 | s_ram_xbar_cmd.str().c_str(), // name |
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| 408 | mt_ram, // mapping table |
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| 409 | x_id, y_id, // x, y |
---|
| 410 | x_width, y_width, l_width, // x_width, y_width, l_width |
---|
| 411 | 2, 0, // local inputs, local outputs |
---|
| 412 | 2, 2, // in fifo, out fifo depths |
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| 413 | true, // is cmd ? |
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| 414 | false, // use routing table ? |
---|
| 415 | false); // support broadcast ? |
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| 416 | |
---|
| 417 | std::ostringstream s_ram_xbar_rsp; |
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| 418 | s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id; |
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| 419 | ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>( |
---|
| 420 | s_ram_xbar_rsp.str().c_str(), // name |
---|
| 421 | mt_ram, // mapping table |
---|
| 422 | x_id, y_id, // x, y |
---|
| 423 | x_width, y_width, l_width, // x_width, y_width, l_width |
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| 424 | 0, 2, // local inputs, local outputs |
---|
| 425 | 2, 2, // in fifo, out fifo depths |
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| 426 | false, // is cmd ? |
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| 427 | true, // use routing table ? |
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| 428 | false); // support broadcast ? |
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| 429 | } // end if IO |
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| 430 | |
---|
| 431 | //////////////////////////////////// |
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| 432 | // Connections are defined here |
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| 433 | //////////////////////////////////// |
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| 434 | |
---|
| 435 | // on coherence network : local srcid[proc] in [0...nb_procs-1] |
---|
| 436 | // : local srcid[memc] = nb_procs |
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[806] | 437 | |
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[747] | 438 | //////////////////////// internal CMD & RSP routers |
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[851] | 439 | for(int k = 0; k < 3; k++) |
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[747] | 440 | { |
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[851] | 441 | int_router_cmd[k]->p_clk (this->p_clk); |
---|
| 442 | int_router_cmd[k]->p_resetn (this->p_resetn); |
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[931] | 443 | int_router_cmd[k]->bind_recovery_port (signal_cfg_router_cmd[k]); |
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[851] | 444 | for (int i = 0; i < 4; i++) |
---|
[747] | 445 | { |
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[851] | 446 | int_router_cmd[k]->p_out[i] (this->p_dspin_int_cmd_out[i][k]); |
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| 447 | int_router_cmd[k]->p_in[i] (this->p_dspin_int_cmd_in[i][k]); |
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[747] | 448 | } |
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[851] | 449 | } |
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[747] | 450 | |
---|
[851] | 451 | for(int k = 0; k < 2; k++) |
---|
| 452 | { |
---|
| 453 | int_router_rsp[k]->p_clk (this->p_clk); |
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| 454 | int_router_rsp[k]->p_resetn (this->p_resetn); |
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[931] | 455 | int_router_rsp[k]->bind_recovery_port (signal_cfg_router_rsp[k]); |
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[851] | 456 | for (int i = 0; i < 4; i++) |
---|
[747] | 457 | { |
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[851] | 458 | int_router_rsp[k]->p_out[i] (this->p_dspin_int_rsp_out[i][k]); |
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| 459 | int_router_rsp[k]->p_in[i] (this->p_dspin_int_rsp_in[i][k]); |
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[747] | 460 | } |
---|
| 461 | } |
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| 462 | |
---|
| 463 | // local ports |
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[851] | 464 | int_router_cmd[0]->p_out[4] (signal_int_dspin_cmd_g2l_d); |
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| 465 | int_router_cmd[1]->p_out[4] (signal_int_dspin_m2p_g2l_c); |
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| 466 | int_router_cmd[2]->p_out[4] (signal_int_dspin_clack_g2l_c); |
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| 467 | int_router_cmd[0]->p_in[4] (signal_int_dspin_cmd_l2g_d); |
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| 468 | int_router_cmd[1]->p_in[4] (signal_int_dspin_m2p_l2g_c); |
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| 469 | int_router_cmd[2]->p_in[4] (signal_int_dspin_clack_l2g_c); |
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[806] | 470 | |
---|
[851] | 471 | int_router_rsp[0]->p_out[4] (signal_int_dspin_rsp_g2l_d); |
---|
| 472 | int_router_rsp[1]->p_out[4] (signal_int_dspin_p2m_g2l_c); |
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| 473 | int_router_rsp[0]->p_in[4] (signal_int_dspin_rsp_l2g_d); |
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| 474 | int_router_rsp[1]->p_in[4] (signal_int_dspin_p2m_l2g_c); |
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[747] | 475 | |
---|
[1001] | 476 | ///////////////////// CMD & RSP local crossbar |
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[747] | 477 | int_xbar_d->p_clk (this->p_clk); |
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| 478 | int_xbar_d->p_resetn (this->p_resetn); |
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[1001] | 479 | (*int_xbar_d->p_barrier_enable) (signal_cfg_xbar_barrier); |
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[747] | 480 | int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); |
---|
| 481 | int_xbar_d->p_target_to_up (signal_int_vci_g2l); |
---|
| 482 | |
---|
| 483 | int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc); |
---|
| 484 | int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); |
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| 485 | int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma); |
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[926] | 486 | int_xbar_d->p_to_target[int_drom_tgt_id] (signal_int_vci_tgt_drom); |
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[747] | 487 | int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma); |
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| 488 | for (size_t p = 0; p < nb_procs; p++) |
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| 489 | int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]); |
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| 490 | |
---|
| 491 | if ( is_io ) |
---|
| 492 | { |
---|
| 493 | int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx); |
---|
| 494 | int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx); |
---|
| 495 | } |
---|
| 496 | |
---|
| 497 | int_wi_gate_d->p_clk (this->p_clk); |
---|
| 498 | int_wi_gate_d->p_resetn (this->p_resetn); |
---|
| 499 | int_wi_gate_d->p_vci (signal_int_vci_l2g); |
---|
| 500 | int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); |
---|
| 501 | int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); |
---|
| 502 | |
---|
| 503 | int_wt_gate_d->p_clk (this->p_clk); |
---|
| 504 | int_wt_gate_d->p_resetn (this->p_resetn); |
---|
| 505 | int_wt_gate_d->p_vci (signal_int_vci_g2l); |
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| 506 | int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); |
---|
| 507 | int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); |
---|
[806] | 508 | |
---|
[747] | 509 | ////////////////////// M2P DSPIN local crossbar coherence |
---|
| 510 | int_xbar_m2p_c->p_clk (this->p_clk); |
---|
| 511 | int_xbar_m2p_c->p_resetn (this->p_resetn); |
---|
[1001] | 512 | (*int_xbar_m2p_c->p_barrier_enable) (signal_cfg_xbar_barrier); |
---|
[747] | 513 | int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); |
---|
| 514 | int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); |
---|
| 515 | int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); |
---|
[806] | 516 | for (size_t p = 0; p < nb_procs; p++) |
---|
[747] | 517 | int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); |
---|
| 518 | |
---|
| 519 | ////////////////////////// P2M DSPIN local crossbar coherence |
---|
| 520 | int_xbar_p2m_c->p_clk (this->p_clk); |
---|
| 521 | int_xbar_p2m_c->p_resetn (this->p_resetn); |
---|
[1001] | 522 | (*int_xbar_p2m_c->p_barrier_enable) (signal_cfg_xbar_barrier); |
---|
[747] | 523 | int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); |
---|
| 524 | int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); |
---|
| 525 | int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); |
---|
[806] | 526 | for (size_t p = 0; p < nb_procs; p++) |
---|
[747] | 527 | int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); |
---|
| 528 | |
---|
| 529 | ////////////////////// CLACK DSPIN local crossbar coherence |
---|
| 530 | int_xbar_clack_c->p_clk (this->p_clk); |
---|
| 531 | int_xbar_clack_c->p_resetn (this->p_resetn); |
---|
[1001] | 532 | (*int_xbar_clack_c->p_barrier_enable) (signal_cfg_xbar_barrier); |
---|
[747] | 533 | int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); |
---|
| 534 | int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); |
---|
| 535 | int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); |
---|
| 536 | for (size_t p = 0; p < nb_procs; p++) |
---|
| 537 | int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); |
---|
| 538 | |
---|
| 539 | //////////////////////////////////// Processors |
---|
[1015] | 540 | for (size_t p = 0; p < nb_procs && !m_disable_procs; p++) |
---|
[747] | 541 | { |
---|
| 542 | proc[p]->p_clk (this->p_clk); |
---|
| 543 | proc[p]->p_resetn (this->p_resetn); |
---|
| 544 | proc[p]->p_vci (signal_int_vci_ini_proc[p]); |
---|
| 545 | proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); |
---|
| 546 | proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); |
---|
| 547 | proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); |
---|
| 548 | |
---|
| 549 | for ( size_t j = 0 ; j < 6 ; j++) |
---|
| 550 | { |
---|
[963] | 551 | if ( j < irq_per_proc ) |
---|
| 552 | { |
---|
| 553 | proc[p]->p_irq[j] (signal_proc_it[irq_per_proc*p + j]); |
---|
| 554 | } |
---|
| 555 | else |
---|
| 556 | { |
---|
[1001] | 557 | proc[p]->p_irq[j] (this->p_false); |
---|
[963] | 558 | } |
---|
[747] | 559 | } |
---|
| 560 | } |
---|
| 561 | |
---|
| 562 | ///////////////////////////////////// XICU |
---|
| 563 | xicu->p_clk (this->p_clk); |
---|
| 564 | xicu->p_resetn (this->p_resetn); |
---|
| 565 | xicu->p_vci (signal_int_vci_tgt_xicu); |
---|
[961] | 566 | for ( size_t i=0 ; i < xcu_nb_out ; i++) |
---|
[747] | 567 | { |
---|
| 568 | xicu->p_irq[i] (signal_proc_it[i]); |
---|
| 569 | } |
---|
[961] | 570 | for ( size_t i=0 ; i < xcu_nb_hwi ; i++) |
---|
[747] | 571 | { |
---|
| 572 | if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc); |
---|
| 573 | else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); |
---|
[1001] | 574 | else xicu->p_hwi[i] (this->p_false); |
---|
[806] | 575 | } |
---|
[904] | 576 | xicu->p_cfg[0] (signal_cfg_router_cmd[0]); // CMD |
---|
| 577 | xicu->p_cfg[1] (signal_cfg_router_rsp[0]); // RSP |
---|
| 578 | xicu->p_cfg[2] (signal_cfg_router_cmd[1]); // M2P |
---|
| 579 | xicu->p_cfg[3] (signal_cfg_router_rsp[1]); // P2M |
---|
| 580 | xicu->p_cfg[4] (signal_cfg_router_cmd[2]); // CLACK |
---|
[1001] | 581 | xicu->p_cfg[5] (signal_cfg_xbar_barrier); // CLACK |
---|
[747] | 582 | |
---|
| 583 | ///////////////////////////////////// MEMC |
---|
| 584 | memc->p_clk (this->p_clk); |
---|
| 585 | memc->p_resetn (this->p_resetn); |
---|
| 586 | memc->p_vci_ixr (signal_ram_vci_ini_memc); |
---|
| 587 | memc->p_vci_tgt (signal_int_vci_tgt_memc); |
---|
| 588 | memc->p_dspin_p2m (signal_int_dspin_p2m_memc); |
---|
| 589 | memc->p_dspin_m2p (signal_int_dspin_m2p_memc); |
---|
| 590 | memc->p_dspin_clack (signal_int_dspin_clack_memc); |
---|
| 591 | memc->p_irq (signal_irq_memc); |
---|
| 592 | |
---|
| 593 | // wrapper to RAM network |
---|
| 594 | memc_ram_wi->p_clk (this->p_clk); |
---|
| 595 | memc_ram_wi->p_resetn (this->p_resetn); |
---|
| 596 | memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); |
---|
| 597 | memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); |
---|
| 598 | memc_ram_wi->p_vci (signal_ram_vci_ini_memc); |
---|
| 599 | |
---|
| 600 | //////////////////////////////////// XRAM |
---|
| 601 | xram->p_clk (this->p_clk); |
---|
| 602 | xram->p_resetn (this->p_resetn); |
---|
| 603 | xram->p_vci (signal_ram_vci_tgt_xram); |
---|
| 604 | |
---|
| 605 | // wrapper to RAM network |
---|
| 606 | xram_ram_wt->p_clk (this->p_clk); |
---|
| 607 | xram_ram_wt->p_resetn (this->p_resetn); |
---|
| 608 | xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); |
---|
| 609 | xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); |
---|
| 610 | xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); |
---|
| 611 | |
---|
| 612 | /////////////////////////////////// MDMA |
---|
| 613 | mdma->p_clk (this->p_clk); |
---|
| 614 | mdma->p_resetn (this->p_resetn); |
---|
| 615 | mdma->p_vci_target (signal_int_vci_tgt_mdma); |
---|
| 616 | mdma->p_vci_initiator (signal_int_vci_ini_mdma); |
---|
| 617 | for (size_t i=0 ; i<nb_dmas ; i++) |
---|
| 618 | mdma->p_irq[i] (signal_irq_mdma[i]); |
---|
| 619 | |
---|
[926] | 620 | /////////////////////////////////// DROM |
---|
| 621 | drom->p_clk (this->p_clk); |
---|
| 622 | drom->p_resetn (this->p_resetn); |
---|
| 623 | drom->p_vci (signal_int_vci_tgt_drom); |
---|
[748] | 624 | |
---|
[747] | 625 | //////////////////////////// RAM network CMD & RSP routers |
---|
| 626 | ram_router_cmd->p_clk (this->p_clk); |
---|
| 627 | ram_router_cmd->p_resetn (this->p_resetn); |
---|
| 628 | ram_router_rsp->p_clk (this->p_clk); |
---|
| 629 | ram_router_rsp->p_resetn (this->p_resetn); |
---|
| 630 | for( size_t n=0 ; n<4 ; n++) |
---|
| 631 | { |
---|
| 632 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
---|
| 633 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
---|
| 634 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
---|
| 635 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
---|
| 636 | } |
---|
| 637 | |
---|
| 638 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); |
---|
| 639 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); |
---|
| 640 | |
---|
| 641 | if ( is_io ) |
---|
| 642 | { |
---|
| 643 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar); |
---|
| 644 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar); |
---|
| 645 | } |
---|
| 646 | else |
---|
| 647 | { |
---|
| 648 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); |
---|
| 649 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); |
---|
| 650 | } |
---|
[806] | 651 | |
---|
| 652 | ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. |
---|
[747] | 653 | if ( is_io ) |
---|
| 654 | { |
---|
| 655 | // IO bridge |
---|
| 656 | iob->p_clk (this->p_clk); |
---|
| 657 | iob->p_resetn (this->p_resetn); |
---|
| 658 | iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); |
---|
| 659 | iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); |
---|
| 660 | iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); |
---|
| 661 | iob->p_vci_ini_int (signal_int_vci_ini_iobx); |
---|
| 662 | iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); |
---|
| 663 | |
---|
| 664 | // initiator wrapper to RAM network |
---|
| 665 | iob_ram_wi->p_clk (this->p_clk); |
---|
| 666 | iob_ram_wi->p_resetn (this->p_resetn); |
---|
| 667 | iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i); |
---|
| 668 | iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i); |
---|
| 669 | iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); |
---|
| 670 | |
---|
| 671 | // crossbar between MEMC and IOB to RAM network |
---|
| 672 | ram_xbar_cmd->p_clk (this->p_clk); |
---|
| 673 | ram_xbar_cmd->p_resetn (this->p_resetn); |
---|
| 674 | ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar); |
---|
| 675 | ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false); |
---|
| 676 | ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i); |
---|
| 677 | ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i); |
---|
| 678 | |
---|
| 679 | ram_xbar_rsp->p_clk (this->p_clk); |
---|
| 680 | ram_xbar_rsp->p_resetn (this->p_resetn); |
---|
| 681 | ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false); |
---|
| 682 | ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar); |
---|
| 683 | ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i); |
---|
| 684 | ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i); |
---|
| 685 | } |
---|
| 686 | |
---|
| 687 | SC_METHOD(init); |
---|
| 688 | |
---|
| 689 | } // end constructor |
---|
| 690 | |
---|
| 691 | tmpl(void)::init() |
---|
| 692 | { |
---|
[1015] | 693 | for (size_t p = 0; p < m_nb_procs && m_disable_procs; p++) |
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| 694 | { |
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| 695 | signal_int_vci_ini_proc[p].cmdval = false; |
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| 696 | signal_int_vci_ini_proc[p].rspack = true; |
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| 697 | signal_int_dspin_m2p_proc[p].read = true; |
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| 698 | signal_int_dspin_p2m_proc[p].write = false; |
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| 699 | signal_int_dspin_clack_proc[p].write = false; |
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| 700 | } |
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| 701 | |
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| 702 | signal_ram_dspin_cmd_false.write = false; |
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| 703 | signal_ram_dspin_rsp_false.read = true; |
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[747] | 704 | } // end init |
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| 705 | |
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[851] | 706 | tmpl(/**/)::~TsarIobCluster() |
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| 707 | { |
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| 708 | for (int k = 0; k < 3; k++) |
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| 709 | { |
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| 710 | delete int_router_cmd[k]; |
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| 711 | } |
---|
| 712 | delete [] int_router_cmd; |
---|
| 713 | |
---|
| 714 | for (int k = 0; k < 2; k++) |
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| 715 | { |
---|
| 716 | delete int_router_rsp[k]; |
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| 717 | } |
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| 718 | delete [] int_router_rsp; |
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| 719 | } |
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| 720 | |
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[747] | 721 | }} |
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| 722 | |
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| 723 | |
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| 724 | // Local Variables: |
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[748] | 725 | // tab-width: 4 |
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| 726 | // c-basic-offset: 4 |
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[747] | 727 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 728 | // indent-tabs-mode: nil |
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| 729 | // End: |
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| 730 | |
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[748] | 731 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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[747] | 732 | |
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