[747] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.cpp |
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[806] | 3 | // Author: Alain Greiner |
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[747] | 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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[806] | 8 | // Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components. |
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[747] | 9 | // These two clusters contain 6 extra components: |
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| 10 | // - 1 vci_io_bridge (connected to the 3 networks. |
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| 11 | // - 3 vci_dspin_wrapper for the IOB. |
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[806] | 12 | // - 2 dspin_local_crossbar for commands and responses. |
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[747] | 13 | ////////////////////////////////////////////////////////////////////////////// |
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| 14 | |
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| 15 | #include "../include/tsar_iob_cluster.h" |
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| 16 | |
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| 17 | #define tmpl(x) \ |
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| 18 | template<typename vci_param_int , typename vci_param_ext,\ |
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| 19 | size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\ |
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| 20 | size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\ |
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| 21 | x TsarIobCluster<\ |
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| 22 | vci_param_int , vci_param_ext,\ |
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| 23 | dspin_int_cmd_width, dspin_int_rsp_width,\ |
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| 24 | dspin_ram_cmd_width, dspin_ram_rsp_width> |
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| 25 | |
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| 26 | namespace soclib { namespace caba { |
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| 27 | |
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| 28 | ////////////////////////////////////////////////////////////////////////// |
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| 29 | // Constructor |
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| 30 | ////////////////////////////////////////////////////////////////////////// |
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| 31 | tmpl(/**/)::TsarIobCluster( |
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[806] | 32 | sc_module_name insname, |
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| 33 | size_t nb_procs, |
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| 34 | size_t nb_dmas, |
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| 35 | size_t x_id, |
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| 36 | size_t y_id, |
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| 37 | size_t x_size, |
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| 38 | size_t y_size, |
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[747] | 39 | |
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[806] | 40 | size_t p_width, |
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[747] | 41 | |
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[806] | 42 | const soclib::common::MappingTable &mt_int, |
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| 43 | const soclib::common::MappingTable &mt_ram, |
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| 44 | const soclib::common::MappingTable &mt_iox, |
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[747] | 45 | |
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[806] | 46 | size_t x_width, |
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| 47 | size_t y_width, |
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| 48 | size_t l_width, |
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[747] | 49 | |
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[806] | 50 | size_t int_memc_tgt_id, // local index |
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| 51 | size_t int_xicu_tgt_id, // local index |
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| 52 | size_t int_mdma_tgt_id, // local index |
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| 53 | size_t int_brom_tgt_id, // local index |
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| 54 | size_t int_iobx_tgt_id, // local index |
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[747] | 55 | |
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[806] | 56 | size_t int_proc_ini_id, // local index |
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| 57 | size_t int_mdma_ini_id, // local index |
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| 58 | size_t int_iobx_ini_id, // local index |
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[747] | 59 | |
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[806] | 60 | size_t ram_xram_tgt_id, // local index |
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| 61 | size_t ram_memc_ini_id, // local index |
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| 62 | size_t ram_iobx_ini_id, // local index |
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[747] | 63 | |
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[806] | 64 | bool is_io, // is IO cluster (IOB)? |
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| 65 | size_t iox_iobx_tgt_id, // local_index |
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| 66 | size_t iox_iobx_ini_id, // local index |
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[747] | 67 | |
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[806] | 68 | size_t memc_ways, |
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| 69 | size_t memc_sets, |
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| 70 | size_t l1_i_ways, |
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| 71 | size_t l1_i_sets, |
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| 72 | size_t l1_d_ways, |
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| 73 | size_t l1_d_sets, |
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| 74 | size_t xram_latency, |
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| 75 | size_t xcu_nb_inputs, |
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[747] | 76 | |
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[806] | 77 | bool distboot, |
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[748] | 78 | |
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[806] | 79 | const Loader &loader, |
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| 80 | |
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| 81 | uint32_t frozen_cycles, |
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| 82 | uint32_t debug_start_cycle, |
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| 83 | bool memc_debug_ok, |
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| 84 | bool proc_debug_ok, |
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| 85 | bool iob_debug_ok ) : |
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| 86 | |
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| 87 | // constructor initialization list |
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| 88 | |
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| 89 | soclib::caba::BaseModule(insname), |
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| 90 | p_clk("clk"), |
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| 91 | p_resetn("resetn") |
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[747] | 92 | { |
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| 93 | |
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[806] | 94 | assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates"); |
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[747] | 95 | |
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[806] | 96 | size_t cluster_id = (x_id << x_width) | y_id; |
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| 97 | |
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[747] | 98 | // Vectors of DSPIN ports for inter-cluster communications |
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| 99 | p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); |
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| 100 | p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3); |
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| 101 | p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2); |
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| 102 | p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2); |
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| 103 | |
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| 104 | p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); |
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| 105 | p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); |
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| 106 | p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); |
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| 107 | p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); |
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| 108 | |
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| 109 | // VCI ports from IOB to IOX network (only in IO clusters) |
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[806] | 110 | if (is_io) |
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[747] | 111 | { |
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| 112 | p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; |
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[806] | 113 | p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; |
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[747] | 114 | } |
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| 115 | |
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| 116 | ///////////////////////////////////////////////////////////////////////////// |
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| 117 | // Hardware components |
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| 118 | ///////////////////////////////////////////////////////////////////////////// |
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| 119 | |
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| 120 | //////////// PROCS |
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| 121 | for (size_t p = 0; p < nb_procs; p++) |
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[806] | 122 | { |
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[747] | 123 | std::ostringstream s_proc; |
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| 124 | s_proc << "proc_" << x_id << "_" << y_id << "_" << p; |
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| 125 | proc[p] = new VciCcVCacheWrapper<vci_param_int, |
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| 126 | dspin_int_cmd_width, |
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| 127 | dspin_int_rsp_width, |
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| 128 | GdbServer<Mips32ElIss> >( |
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| 129 | s_proc.str().c_str(), |
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[806] | 130 | (cluster_id << p_width) | p, // GLOBAL PROC_ID |
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[747] | 131 | mt_int, // Mapping Table INT network |
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| 132 | IntTab(cluster_id,p), // SRCID |
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[806] | 133 | (cluster_id << l_width) | p, // CC_GLOBAL_ID |
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[747] | 134 | 8, // ITLB ways |
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| 135 | 8, // ITLB sets |
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| 136 | 8, // DTLB ways |
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| 137 | 8, // DTLB sets |
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| 138 | l1_i_ways, l1_i_sets, 16, // ICACHE size |
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| 139 | l1_d_ways, l1_d_sets, 16, // DCACHE size |
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| 140 | 4, // WBUF nlines |
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| 141 | 4, // WBUF nwords |
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[806] | 142 | x_width, // number of bits for x coordinate |
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| 143 | y_width, // number of bits for y coordinate |
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[747] | 144 | frozen_cycles, // max frozen cycles |
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| 145 | debug_start_cycle, |
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| 146 | proc_debug_ok); |
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[748] | 147 | |
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| 148 | // initialize physical address extension with cluster ID when using |
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| 149 | // distributed boot |
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| 150 | if (distboot) |
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| 151 | { |
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| 152 | proc[p]->set_dcache_paddr_ext_reset(cluster_id); |
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| 153 | proc[p]->set_icache_paddr_ext_reset(cluster_id); |
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| 154 | } |
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[747] | 155 | } |
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| 156 | |
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[806] | 157 | /////////// MEMC |
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[747] | 158 | std::ostringstream s_memc; |
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| 159 | s_memc << "memc_" << x_id << "_" << y_id; |
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| 160 | memc = new VciMemCache<vci_param_int, |
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| 161 | vci_param_ext, |
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| 162 | dspin_int_rsp_width, |
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| 163 | dspin_int_cmd_width>( |
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| 164 | s_memc.str().c_str(), |
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| 165 | mt_int, // Mapping Table INT network |
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| 166 | mt_ram, // Mapping Table RAM network |
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| 167 | IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network |
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| 168 | IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network |
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| 169 | x_width, // number of bits for x coordinate |
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| 170 | y_width, // number of bits for y coordinate |
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| 171 | memc_ways, memc_sets, 16, // CACHE SIZE |
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| 172 | 3, // MAX NUMBER OF COPIES |
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| 173 | 4096, // HEAP SIZE |
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| 174 | 8, // TRANSACTION TABLE DEPTH |
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| 175 | 8, // UPDATE TABLE DEPTH |
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| 176 | 8, // INVALIDATE TABLE DEPTH |
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| 177 | debug_start_cycle, |
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| 178 | memc_debug_ok ); |
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| 179 | |
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| 180 | std::ostringstream s_wi_memc; |
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| 181 | s_wi_memc << "memc_wi_" << x_id << "_" << y_id; |
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| 182 | memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 183 | dspin_ram_cmd_width, |
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| 184 | dspin_ram_rsp_width>( |
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| 185 | s_wi_memc.str().c_str(), |
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| 186 | x_width + y_width + l_width); |
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| 187 | |
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| 188 | /////////// XICU |
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| 189 | std::ostringstream s_xicu; |
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| 190 | s_xicu << "xicu_" << x_id << "_" << y_id; |
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| 191 | xicu = new VciXicu<vci_param_int>( |
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| 192 | s_xicu.str().c_str(), |
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| 193 | mt_int, // mapping table INT network |
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| 194 | IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space |
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| 195 | xcu_nb_inputs, // number of timer IRQs |
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| 196 | xcu_nb_inputs, // number of hard IRQs |
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| 197 | xcu_nb_inputs, // number of soft IRQs |
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| 198 | 16); // number of output IRQs |
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| 199 | |
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| 200 | //////////// MDMA |
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| 201 | std::ostringstream s_mdma; |
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| 202 | s_mdma << "mdma_" << x_id << "_" << y_id; |
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| 203 | mdma = new VciMultiDma<vci_param_int>( |
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| 204 | s_mdma.str().c_str(), |
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| 205 | mt_int, |
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| 206 | IntTab(cluster_id, nb_procs), // SRCID |
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| 207 | IntTab(cluster_id, int_mdma_tgt_id), // TGTID |
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| 208 | 64, // burst size |
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| 209 | nb_dmas); // number of IRQs |
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| 210 | |
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[748] | 211 | /////////// DISTRIBUTED BOOT ROM |
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| 212 | std::ostringstream s_brom; |
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| 213 | s_brom << "brom_" << x_id << "_" << y_id; |
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| 214 | brom = new VciSimpleRom<vci_param_int>( |
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| 215 | s_brom.str().c_str(), |
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| 216 | IntTab(cluster_id, int_brom_tgt_id), |
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| 217 | mt_int, |
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| 218 | loader, |
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| 219 | x_width + y_width); // msb drop bits |
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| 220 | |
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[747] | 221 | /////////// Direct LOCAL_XBAR(S) |
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| 222 | size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1; |
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[748] | 223 | size_t nb_direct_targets = is_io ? 5 : 4; |
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[747] | 224 | |
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| 225 | std::ostringstream s_int_xbar_d; |
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| 226 | s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; |
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| 227 | int_xbar_d = new VciLocalCrossbar<vci_param_int>( |
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| 228 | s_int_xbar_d.str().c_str(), |
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| 229 | mt_int, // mapping table |
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| 230 | cluster_id, // cluster id |
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| 231 | nb_direct_initiators, // number of local initiators |
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[806] | 232 | nb_direct_targets, // number of local targets |
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[747] | 233 | 0 ); // default target |
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| 234 | |
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| 235 | std::ostringstream s_int_dspin_ini_wrapper_gate_d; |
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| 236 | s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_" |
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| 237 | << x_id << "_" << y_id; |
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| 238 | int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int, |
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| 239 | dspin_int_cmd_width, |
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| 240 | dspin_int_rsp_width>( |
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| 241 | s_int_dspin_ini_wrapper_gate_d.str().c_str(), |
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| 242 | x_width + y_width + l_width); |
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| 243 | |
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| 244 | std::ostringstream s_int_dspin_tgt_wrapper_gate_d; |
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| 245 | s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_" |
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| 246 | << x_id << "_" << y_id; |
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| 247 | int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int, |
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| 248 | dspin_int_cmd_width, |
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| 249 | dspin_int_rsp_width>( |
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| 250 | s_int_dspin_tgt_wrapper_gate_d.str().c_str(), |
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| 251 | x_width + y_width + l_width); |
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| 252 | |
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| 253 | //////////// Coherence LOCAL_XBAR(S) |
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| 254 | std::ostringstream s_int_xbar_m2p_c; |
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| 255 | s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; |
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| 256 | int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 257 | s_int_xbar_m2p_c.str().c_str(), |
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| 258 | mt_int, // mapping table |
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| 259 | x_id, y_id, // cluster coordinates |
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| 260 | x_width, y_width, l_width, // several dests |
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| 261 | 1, // number of local sources |
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[806] | 262 | nb_procs, // number of local dests |
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| 263 | 2, 2, // fifo depths |
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[747] | 264 | true, // pseudo CMD |
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| 265 | false, // no routing table |
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| 266 | true ); // broacast |
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| 267 | |
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| 268 | std::ostringstream s_int_xbar_p2m_c; |
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| 269 | s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; |
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| 270 | int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 271 | s_int_xbar_p2m_c.str().c_str(), |
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| 272 | mt_int, // mapping table |
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| 273 | x_id, y_id, // cluster coordinates |
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| 274 | x_width, y_width, 0, // only one dest |
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| 275 | nb_procs, // number of local sources |
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| 276 | 1, // number of local dests |
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[806] | 277 | 2, 2, // fifo depths |
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[747] | 278 | false, // pseudo RSP |
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| 279 | false, // no routing table |
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[806] | 280 | false ); // no broacast |
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[747] | 281 | |
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| 282 | std::ostringstream s_int_xbar_clack_c; |
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| 283 | s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; |
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| 284 | int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 285 | s_int_xbar_clack_c.str().c_str(), |
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| 286 | mt_int, // mapping table |
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| 287 | x_id, y_id, // cluster coordinates |
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| 288 | x_width, y_width, l_width, |
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| 289 | 1, // number of local sources |
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[806] | 290 | nb_procs, // number of local targets |
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[747] | 291 | 1, 1, // fifo depths |
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| 292 | true, // CMD |
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| 293 | false, // no routing table |
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| 294 | false); // broadcast |
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| 295 | |
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| 296 | ////////////// INT ROUTER(S) |
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| 297 | std::ostringstream s_int_router_cmd; |
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| 298 | s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id; |
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| 299 | int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>( |
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| 300 | s_int_router_cmd.str().c_str(), |
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| 301 | x_id,y_id, // coordinate in the mesh |
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| 302 | x_width, y_width, // x & y fields width |
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| 303 | 3, // nb virtual channels |
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[806] | 304 | 4, 4); // input & output fifo depths |
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[747] | 305 | |
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| 306 | std::ostringstream s_int_router_rsp; |
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| 307 | s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id; |
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| 308 | int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( |
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| 309 | s_int_router_rsp.str().c_str(), |
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| 310 | x_id,y_id, // router coordinates in mesh |
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| 311 | x_width, y_width, // x & y fields width |
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| 312 | 2, // nb virtual channels |
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[806] | 313 | 4, 4); // input & output fifo depths |
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[747] | 314 | |
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| 315 | ////////////// XRAM |
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| 316 | std::ostringstream s_xram; |
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| 317 | s_xram << "xram_" << x_id << "_" << y_id; |
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| 318 | xram = new VciSimpleRam<vci_param_ext>( |
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| 319 | s_xram.str().c_str(), |
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| 320 | IntTab(cluster_id, ram_xram_tgt_id), |
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| 321 | mt_ram, |
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| 322 | loader, |
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| 323 | xram_latency); |
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| 324 | |
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| 325 | std::ostringstream s_wt_xram; |
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| 326 | s_wt_xram << "xram_wt_" << x_id << "_" << y_id; |
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| 327 | xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext, |
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| 328 | dspin_ram_cmd_width, |
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| 329 | dspin_ram_rsp_width>( |
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| 330 | s_wt_xram.str().c_str(), |
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| 331 | x_width + y_width + l_width); |
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| 332 | |
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| 333 | ///////////// RAM ROUTER(S) |
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| 334 | std::ostringstream s_ram_router_cmd; |
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| 335 | s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; |
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| 336 | ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>( |
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| 337 | s_ram_router_cmd.str().c_str(), |
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| 338 | x_id, y_id, // router coordinates in mesh |
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| 339 | x_width, // x field width in first flit |
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| 340 | y_width, // y field width in first flit |
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| 341 | 4, 4); // input & output fifo depths |
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| 342 | |
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| 343 | std::ostringstream s_ram_router_rsp; |
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| 344 | s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; |
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| 345 | ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>( |
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| 346 | s_ram_router_rsp.str().c_str(), |
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| 347 | x_id, y_id, // coordinates in mesh |
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| 348 | x_width, // x field width in first flit |
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| 349 | y_width, // y field width in first flit |
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| 350 | 4, 4); // input & output fifo depths |
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| 351 | |
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| 352 | |
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| 353 | ////////////////////// I/O CLUSTER ONLY /////////////////////// |
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| 354 | if ( is_io ) |
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| 355 | { |
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| 356 | /////////// IO_BRIDGE |
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| 357 | std::ostringstream s_iob; |
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[806] | 358 | s_iob << "iob_" << x_id << "_" << y_id; |
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[747] | 359 | iob = new VciIoBridge<vci_param_int, |
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[806] | 360 | vci_param_ext>( |
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[747] | 361 | s_iob.str().c_str(), |
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| 362 | mt_ram, // EXT network maptab |
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| 363 | mt_int, // INT network maptab |
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| 364 | mt_iox, // IOX network maptab |
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| 365 | IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID |
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| 366 | IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID |
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| 367 | IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID |
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| 368 | IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID |
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| 369 | 16, // cache line words |
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| 370 | 8, // IOTLB ways |
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| 371 | 8, // IOTLB sets |
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| 372 | debug_start_cycle, |
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| 373 | iob_debug_ok ); |
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[806] | 374 | |
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[747] | 375 | std::ostringstream s_iob_ram_wi; |
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[806] | 376 | s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; |
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[747] | 377 | iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 378 | dspin_ram_cmd_width, |
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| 379 | dspin_ram_rsp_width>( |
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| 380 | s_iob_ram_wi.str().c_str(), |
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| 381 | vci_param_int::S); |
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| 382 | |
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| 383 | std::ostringstream s_ram_xbar_cmd; |
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| 384 | s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id; |
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| 385 | ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>( |
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| 386 | s_ram_xbar_cmd.str().c_str(), // name |
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| 387 | mt_ram, // mapping table |
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| 388 | x_id, y_id, // x, y |
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| 389 | x_width, y_width, l_width, // x_width, y_width, l_width |
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| 390 | 2, 0, // local inputs, local outputs |
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| 391 | 2, 2, // in fifo, out fifo depths |
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| 392 | true, // is cmd ? |
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| 393 | false, // use routing table ? |
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| 394 | false); // support broadcast ? |
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| 395 | |
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| 396 | std::ostringstream s_ram_xbar_rsp; |
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| 397 | s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id; |
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| 398 | ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>( |
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| 399 | s_ram_xbar_rsp.str().c_str(), // name |
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| 400 | mt_ram, // mapping table |
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| 401 | x_id, y_id, // x, y |
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| 402 | x_width, y_width, l_width, // x_width, y_width, l_width |
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| 403 | 0, 2, // local inputs, local outputs |
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| 404 | 2, 2, // in fifo, out fifo depths |
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| 405 | false, // is cmd ? |
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| 406 | true, // use routing table ? |
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| 407 | false); // support broadcast ? |
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| 408 | } // end if IO |
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| 409 | |
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| 410 | //////////////////////////////////// |
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| 411 | // Connections are defined here |
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| 412 | //////////////////////////////////// |
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| 413 | |
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| 414 | // on coherence network : local srcid[proc] in [0...nb_procs-1] |
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| 415 | // : local srcid[memc] = nb_procs |
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[806] | 416 | |
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[747] | 417 | //////////////////////// internal CMD & RSP routers |
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| 418 | int_router_cmd->p_clk (this->p_clk); |
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| 419 | int_router_cmd->p_resetn (this->p_resetn); |
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| 420 | int_router_rsp->p_clk (this->p_clk); |
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| 421 | int_router_rsp->p_resetn (this->p_resetn); |
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| 422 | |
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| 423 | for (int i = 0; i < 4; i++) |
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| 424 | { |
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| 425 | for(int k = 0; k < 3; k++) |
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| 426 | { |
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| 427 | int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); |
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| 428 | int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); |
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| 429 | } |
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| 430 | |
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| 431 | for(int k = 0; k < 2; k++) |
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| 432 | { |
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| 433 | int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); |
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| 434 | int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); |
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| 435 | } |
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| 436 | } |
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| 437 | |
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| 438 | // local ports |
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| 439 | int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); |
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| 440 | int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); |
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| 441 | int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); |
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| 442 | int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); |
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| 443 | int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); |
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| 444 | int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); |
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[806] | 445 | |
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[747] | 446 | int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); |
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| 447 | int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); |
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| 448 | int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); |
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| 449 | int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); |
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| 450 | |
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| 451 | ///////////////////// CMD DSPIN local crossbar direct |
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| 452 | int_xbar_d->p_clk (this->p_clk); |
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| 453 | int_xbar_d->p_resetn (this->p_resetn); |
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| 454 | int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); |
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| 455 | int_xbar_d->p_target_to_up (signal_int_vci_g2l); |
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| 456 | |
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| 457 | int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc); |
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| 458 | int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); |
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| 459 | int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma); |
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[748] | 460 | int_xbar_d->p_to_target[int_brom_tgt_id] (signal_int_vci_tgt_brom); |
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[747] | 461 | int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma); |
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| 462 | for (size_t p = 0; p < nb_procs; p++) |
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| 463 | int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]); |
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| 464 | |
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| 465 | if ( is_io ) |
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| 466 | { |
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| 467 | int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx); |
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| 468 | int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx); |
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| 469 | } |
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| 470 | |
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| 471 | int_wi_gate_d->p_clk (this->p_clk); |
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| 472 | int_wi_gate_d->p_resetn (this->p_resetn); |
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| 473 | int_wi_gate_d->p_vci (signal_int_vci_l2g); |
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| 474 | int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); |
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| 475 | int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); |
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| 476 | |
---|
| 477 | int_wt_gate_d->p_clk (this->p_clk); |
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| 478 | int_wt_gate_d->p_resetn (this->p_resetn); |
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| 479 | int_wt_gate_d->p_vci (signal_int_vci_g2l); |
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| 480 | int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); |
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| 481 | int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); |
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[806] | 482 | |
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[747] | 483 | ////////////////////// M2P DSPIN local crossbar coherence |
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| 484 | int_xbar_m2p_c->p_clk (this->p_clk); |
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| 485 | int_xbar_m2p_c->p_resetn (this->p_resetn); |
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| 486 | int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); |
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| 487 | int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); |
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| 488 | int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); |
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[806] | 489 | for (size_t p = 0; p < nb_procs; p++) |
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[747] | 490 | int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); |
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| 491 | |
---|
| 492 | ////////////////////////// P2M DSPIN local crossbar coherence |
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| 493 | int_xbar_p2m_c->p_clk (this->p_clk); |
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| 494 | int_xbar_p2m_c->p_resetn (this->p_resetn); |
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| 495 | int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); |
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| 496 | int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); |
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| 497 | int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); |
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[806] | 498 | for (size_t p = 0; p < nb_procs; p++) |
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[747] | 499 | int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); |
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| 500 | |
---|
| 501 | ////////////////////// CLACK DSPIN local crossbar coherence |
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| 502 | int_xbar_clack_c->p_clk (this->p_clk); |
---|
| 503 | int_xbar_clack_c->p_resetn (this->p_resetn); |
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| 504 | int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); |
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| 505 | int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); |
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| 506 | int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); |
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| 507 | for (size_t p = 0; p < nb_procs; p++) |
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| 508 | int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); |
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| 509 | |
---|
| 510 | //////////////////////////////////// Processors |
---|
| 511 | for (size_t p = 0; p < nb_procs; p++) |
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| 512 | { |
---|
| 513 | proc[p]->p_clk (this->p_clk); |
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| 514 | proc[p]->p_resetn (this->p_resetn); |
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| 515 | proc[p]->p_vci (signal_int_vci_ini_proc[p]); |
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| 516 | proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); |
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| 517 | proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); |
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| 518 | proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); |
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| 519 | |
---|
| 520 | for ( size_t j = 0 ; j < 6 ; j++) |
---|
| 521 | { |
---|
| 522 | if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]); |
---|
| 523 | else proc[p]->p_irq[j] (signal_false); |
---|
| 524 | } |
---|
| 525 | } |
---|
| 526 | |
---|
| 527 | ///////////////////////////////////// XICU |
---|
| 528 | xicu->p_clk (this->p_clk); |
---|
| 529 | xicu->p_resetn (this->p_resetn); |
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| 530 | xicu->p_vci (signal_int_vci_tgt_xicu); |
---|
| 531 | for ( size_t i=0 ; i < 16 ; i++) |
---|
| 532 | { |
---|
| 533 | xicu->p_irq[i] (signal_proc_it[i]); |
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| 534 | } |
---|
| 535 | for ( size_t i=0 ; i < xcu_nb_inputs ; i++) |
---|
| 536 | { |
---|
| 537 | if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc); |
---|
| 538 | else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); |
---|
| 539 | else xicu->p_hwi[i] (signal_false); |
---|
[806] | 540 | } |
---|
[747] | 541 | |
---|
| 542 | ///////////////////////////////////// MEMC |
---|
| 543 | memc->p_clk (this->p_clk); |
---|
| 544 | memc->p_resetn (this->p_resetn); |
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| 545 | memc->p_vci_ixr (signal_ram_vci_ini_memc); |
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| 546 | memc->p_vci_tgt (signal_int_vci_tgt_memc); |
---|
| 547 | memc->p_dspin_p2m (signal_int_dspin_p2m_memc); |
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| 548 | memc->p_dspin_m2p (signal_int_dspin_m2p_memc); |
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| 549 | memc->p_dspin_clack (signal_int_dspin_clack_memc); |
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| 550 | memc->p_irq (signal_irq_memc); |
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| 551 | |
---|
| 552 | // wrapper to RAM network |
---|
| 553 | memc_ram_wi->p_clk (this->p_clk); |
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| 554 | memc_ram_wi->p_resetn (this->p_resetn); |
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| 555 | memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); |
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| 556 | memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); |
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| 557 | memc_ram_wi->p_vci (signal_ram_vci_ini_memc); |
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| 558 | |
---|
| 559 | //////////////////////////////////// XRAM |
---|
| 560 | xram->p_clk (this->p_clk); |
---|
| 561 | xram->p_resetn (this->p_resetn); |
---|
| 562 | xram->p_vci (signal_ram_vci_tgt_xram); |
---|
| 563 | |
---|
| 564 | // wrapper to RAM network |
---|
| 565 | xram_ram_wt->p_clk (this->p_clk); |
---|
| 566 | xram_ram_wt->p_resetn (this->p_resetn); |
---|
| 567 | xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); |
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| 568 | xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); |
---|
| 569 | xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); |
---|
| 570 | |
---|
| 571 | /////////////////////////////////// MDMA |
---|
| 572 | mdma->p_clk (this->p_clk); |
---|
| 573 | mdma->p_resetn (this->p_resetn); |
---|
| 574 | mdma->p_vci_target (signal_int_vci_tgt_mdma); |
---|
| 575 | mdma->p_vci_initiator (signal_int_vci_ini_mdma); |
---|
| 576 | for (size_t i=0 ; i<nb_dmas ; i++) |
---|
| 577 | mdma->p_irq[i] (signal_irq_mdma[i]); |
---|
| 578 | |
---|
[748] | 579 | /////////////////////////////////// BROM |
---|
| 580 | brom->p_clk (this->p_clk); |
---|
| 581 | brom->p_resetn (this->p_resetn); |
---|
| 582 | brom->p_vci (signal_int_vci_tgt_brom); |
---|
| 583 | |
---|
[747] | 584 | //////////////////////////// RAM network CMD & RSP routers |
---|
| 585 | ram_router_cmd->p_clk (this->p_clk); |
---|
| 586 | ram_router_cmd->p_resetn (this->p_resetn); |
---|
| 587 | ram_router_rsp->p_clk (this->p_clk); |
---|
| 588 | ram_router_rsp->p_resetn (this->p_resetn); |
---|
| 589 | for( size_t n=0 ; n<4 ; n++) |
---|
| 590 | { |
---|
| 591 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
---|
| 592 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
---|
| 593 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
---|
| 594 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
---|
| 595 | } |
---|
| 596 | |
---|
| 597 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); |
---|
| 598 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); |
---|
| 599 | |
---|
| 600 | if ( is_io ) |
---|
| 601 | { |
---|
| 602 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar); |
---|
| 603 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar); |
---|
| 604 | } |
---|
| 605 | else |
---|
| 606 | { |
---|
| 607 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); |
---|
| 608 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); |
---|
| 609 | } |
---|
[806] | 610 | |
---|
| 611 | ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. |
---|
[747] | 612 | if ( is_io ) |
---|
| 613 | { |
---|
| 614 | // IO bridge |
---|
| 615 | iob->p_clk (this->p_clk); |
---|
| 616 | iob->p_resetn (this->p_resetn); |
---|
| 617 | iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); |
---|
| 618 | iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); |
---|
| 619 | iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); |
---|
| 620 | iob->p_vci_ini_int (signal_int_vci_ini_iobx); |
---|
| 621 | iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); |
---|
| 622 | |
---|
| 623 | // initiator wrapper to RAM network |
---|
| 624 | iob_ram_wi->p_clk (this->p_clk); |
---|
| 625 | iob_ram_wi->p_resetn (this->p_resetn); |
---|
| 626 | iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i); |
---|
| 627 | iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i); |
---|
| 628 | iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); |
---|
| 629 | |
---|
| 630 | // crossbar between MEMC and IOB to RAM network |
---|
| 631 | ram_xbar_cmd->p_clk (this->p_clk); |
---|
| 632 | ram_xbar_cmd->p_resetn (this->p_resetn); |
---|
| 633 | ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar); |
---|
| 634 | ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false); |
---|
| 635 | ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i); |
---|
| 636 | ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i); |
---|
| 637 | |
---|
| 638 | ram_xbar_rsp->p_clk (this->p_clk); |
---|
| 639 | ram_xbar_rsp->p_resetn (this->p_resetn); |
---|
| 640 | ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false); |
---|
| 641 | ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar); |
---|
| 642 | ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i); |
---|
| 643 | ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i); |
---|
| 644 | } |
---|
| 645 | |
---|
| 646 | SC_METHOD(init); |
---|
| 647 | |
---|
| 648 | } // end constructor |
---|
| 649 | |
---|
| 650 | tmpl(void)::init() |
---|
| 651 | { |
---|
| 652 | signal_ram_dspin_cmd_false.write = false; |
---|
| 653 | signal_ram_dspin_rsp_false.read = true; |
---|
| 654 | } // end init |
---|
| 655 | |
---|
| 656 | }} |
---|
| 657 | |
---|
| 658 | |
---|
| 659 | // Local Variables: |
---|
[748] | 660 | // tab-width: 4 |
---|
| 661 | // c-basic-offset: 4 |
---|
[747] | 662 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 663 | // indent-tabs-mode: nil |
---|
| 664 | // End: |
---|
| 665 | |
---|
[748] | 666 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
[747] | 667 | |
---|