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source: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 748

Last change on this file since 748 was 748, checked in by cfuguet, 10 years ago

reconfiguration: tsar_generic_iob distributed boot

Introducing optional distributed boot in the tsar_generic_iob platform.

To support this, a distributed boot ROM is instantiated in each cluster.

Physical address extension register for instructions and data of L1 caches is initialized with local cluster index when distributed boot is activated.

File size: 33.6 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define tmpl(x) \
18	template<typename vci_param_int , typename vci_param_ext,\
19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
21	x TsarIobCluster<\
22	vci_param_int , vci_param_ext,\
23	dspin_int_cmd_width, dspin_int_rsp_width,\
24	dspin_ram_cmd_width, dspin_ram_rsp_width>
25
26	namespace soclib { namespace caba {
27
28	//////////////////////////////////////////////////////////////////////////
29	// Constructor
30	//////////////////////////////////////////////////////////////////////////
31	tmpl(/**/)::TsarIobCluster(
32	//////////////////////////////////////////////////////////////////////////
33	sc_module_name insname,
34	size_t nb_procs,
35	size_t nb_dmas,
36	size_t x_id,
37	size_t y_id,
38	size_t xmax,
39	size_t ymax,
40
41	const soclib::common::MappingTable &mt_int,
42	const soclib::common::MappingTable &mt_ram,
43	const soclib::common::MappingTable &mt_iox,
44
45	size_t x_width,
46	size_t y_width,
47	size_t l_width,
48
49	size_t int_memc_tgt_id, // local index
50	size_t int_xicu_tgt_id, // local index
51	size_t int_mdma_tgt_id, // local index
52	size_t int_brom_tgt_id, // local index
53	size_t int_iobx_tgt_id, // local index
54
55	size_t int_proc_ini_id, // local index
56	size_t int_mdma_ini_id, // local index
57	size_t int_iobx_ini_id, // local index
58
59	size_t ram_xram_tgt_id, // local index
60	size_t ram_memc_ini_id, // local index
61	size_t ram_iobx_ini_id, // local index
62
63	bool is_io, // is IO cluster (IOB)?
64	size_t iox_iobx_tgt_id, // local_index
65	size_t iox_iobx_ini_id, // local index
66
67	size_t memc_ways,
68	size_t memc_sets,
69	size_t l1_i_ways,
70	size_t l1_i_sets,
71	size_t l1_d_ways,
72	size_t l1_d_sets,
73	size_t xram_latency,
74	size_t xcu_nb_inputs,
75
76	bool distboot,
77
78	const Loader &loader,
79
80	uint32_t frozen_cycles,
81	uint32_t debug_start_cycle,
82	bool memc_debug_ok,
83	bool proc_debug_ok,
84	bool iob_debug_ok )
85	: soclib::caba::BaseModule(insname),
86	p_clk("clk"),
87	p_resetn("resetn")
88	{
89	assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates");
90
91	size_t cluster_id = (x_id<<4) + y_id;
92
93	// Vectors of DSPIN ports for inter-cluster communications
94	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
95	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
96	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
97	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
98
99	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
100	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
101	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
102	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
103
104	// VCI ports from IOB to IOX network (only in IO clusters)
105	if ( is_io )
106	{
107	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
108	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
109	}
110
111	/////////////////////////////////////////////////////////////////////////////
112	// Hardware components
113	/////////////////////////////////////////////////////////////////////////////
114
115	//////////// PROCS
116	for (size_t p = 0; p < nb_procs; p++)
117	{
118	std::ostringstream s_proc;
119	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
120	proc[p] = new VciCcVCacheWrapper<vci_param_int,
121	dspin_int_cmd_width,
122	dspin_int_rsp_width,
123	GdbServer<Mips32ElIss> >(
124	s_proc.str().c_str(),
125	cluster_id*nb_procs + p, // GLOBAL PROC_ID
126	mt_int, // Mapping Table INT network
127	IntTab(cluster_id,p), // SRCID
128	(cluster_id << l_width) + p, // CC_GLOBAL_ID
129	8, // ITLB ways
130	8, // ITLB sets
131	8, // DTLB ways
132	8, // DTLB sets
133	l1_i_ways, l1_i_sets, 16, // ICACHE size
134	l1_d_ways, l1_d_sets, 16, // DCACHE size
135	4, // WBUF nlines
136	4, // WBUF nwords
137	x_width,
138	y_width,
139	frozen_cycles, // max frozen cycles
140	debug_start_cycle,
141	proc_debug_ok);
142
143	// initialize physical address extension with cluster ID when using
144	// distributed boot
145	if (distboot)
146	{
147	proc[p]->set_dcache_paddr_ext_reset(cluster_id);
148	proc[p]->set_icache_paddr_ext_reset(cluster_id);
149	}
150	}
151
152	/////////// MEMC
153	std::ostringstream s_memc;
154	s_memc << "memc_" << x_id << "_" << y_id;
155	memc = new VciMemCache<vci_param_int,
156	vci_param_ext,
157	dspin_int_rsp_width,
158	dspin_int_cmd_width>(
159	s_memc.str().c_str(),
160	mt_int, // Mapping Table INT network
161	mt_ram, // Mapping Table RAM network
162	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
163	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
164	x_width, // number of bits for x coordinate
165	y_width, // number of bits for y coordinate
166	memc_ways, memc_sets, 16, // CACHE SIZE
167	3, // MAX NUMBER OF COPIES
168	4096, // HEAP SIZE
169	8, // TRANSACTION TABLE DEPTH
170	8, // UPDATE TABLE DEPTH
171	8, // INVALIDATE TABLE DEPTH
172	debug_start_cycle,
173	memc_debug_ok );
174
175	std::ostringstream s_wi_memc;
176	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
177	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
178	dspin_ram_cmd_width,
179	dspin_ram_rsp_width>(
180	s_wi_memc.str().c_str(),
181	x_width + y_width + l_width);
182
183	/////////// XICU
184	std::ostringstream s_xicu;
185	s_xicu << "xicu_" << x_id << "_" << y_id;
186	xicu = new VciXicu<vci_param_int>(
187	s_xicu.str().c_str(),
188	mt_int, // mapping table INT network
189	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
190	xcu_nb_inputs, // number of timer IRQs
191	xcu_nb_inputs, // number of hard IRQs
192	xcu_nb_inputs, // number of soft IRQs
193	16); // number of output IRQs
194
195	//////////// MDMA
196	std::ostringstream s_mdma;
197	s_mdma << "mdma_" << x_id << "_" << y_id;
198	mdma = new VciMultiDma<vci_param_int>(
199	s_mdma.str().c_str(),
200	mt_int,
201	IntTab(cluster_id, nb_procs), // SRCID
202	IntTab(cluster_id, int_mdma_tgt_id), // TGTID
203	64, // burst size
204	nb_dmas); // number of IRQs
205
206	/////////// DISTRIBUTED BOOT ROM
207	std::ostringstream s_brom;
208	s_brom << "brom_" << x_id << "_" << y_id;
209	brom = new VciSimpleRom<vci_param_int>(
210	s_brom.str().c_str(),
211	IntTab(cluster_id, int_brom_tgt_id),
212	mt_int,
213	loader,
214	x_width + y_width); // msb drop bits
215
216	/////////// Direct LOCAL_XBAR(S)
217	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
218	size_t nb_direct_targets = is_io ? 5 : 4;
219
220	std::ostringstream s_int_xbar_d;
221	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
222	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
223	s_int_xbar_d.str().c_str(),
224	mt_int, // mapping table
225	cluster_id, // cluster id
226	nb_direct_initiators, // number of local initiators
227	nb_direct_targets, // number of local targets
228	0 ); // default target
229
230	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
231	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
232	<< x_id << "_" << y_id;
233	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
234	dspin_int_cmd_width,
235	dspin_int_rsp_width>(
236	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
237	x_width + y_width + l_width);
238
239	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
240	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
241	<< x_id << "_" << y_id;
242	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
243	dspin_int_cmd_width,
244	dspin_int_rsp_width>(
245	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
246	x_width + y_width + l_width);
247
248	//////////// Coherence LOCAL_XBAR(S)
249	std::ostringstream s_int_xbar_m2p_c;
250	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
251	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
252	s_int_xbar_m2p_c.str().c_str(),
253	mt_int, // mapping table
254	x_id, y_id, // cluster coordinates
255	x_width, y_width, l_width, // several dests
256	1, // number of local sources
257	nb_procs, // number of local dests
258	2, 2, // fifo depths
259	true, // pseudo CMD
260	false, // no routing table
261	true ); // broacast
262
263	std::ostringstream s_int_xbar_p2m_c;
264	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
265	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
266	s_int_xbar_p2m_c.str().c_str(),
267	mt_int, // mapping table
268	x_id, y_id, // cluster coordinates
269	x_width, y_width, 0, // only one dest
270	nb_procs, // number of local sources
271	1, // number of local dests
272	2, 2, // fifo depths
273	false, // pseudo RSP
274	false, // no routing table
275	false ); // no broacast
276
277	std::ostringstream s_int_xbar_clack_c;
278	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
279	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
280	s_int_xbar_clack_c.str().c_str(),
281	mt_int, // mapping table
282	x_id, y_id, // cluster coordinates
283	x_width, y_width, l_width,
284	1, // number of local sources
285	nb_procs, // number of local targets
286	1, 1, // fifo depths
287	true, // CMD
288	false, // no routing table
289	false); // broadcast
290
291	////////////// INT ROUTER(S)
292	std::ostringstream s_int_router_cmd;
293	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id;
294	int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>(
295	s_int_router_cmd.str().c_str(),
296	x_id,y_id, // coordinate in the mesh
297	x_width, y_width, // x & y fields width
298	3, // nb virtual channels
299	4,4); // input & output fifo depths
300
301	std::ostringstream s_int_router_rsp;
302	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id;
303	int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>(
304	s_int_router_rsp.str().c_str(),
305	x_id,y_id, // router coordinates in mesh
306	x_width, y_width, // x & y fields width
307	2, // nb virtual channels
308	4,4); // input & output fifo depths
309
310	////////////// XRAM
311	std::ostringstream s_xram;
312	s_xram << "xram_" << x_id << "_" << y_id;
313	xram = new VciSimpleRam<vci_param_ext>(
314	s_xram.str().c_str(),
315	IntTab(cluster_id, ram_xram_tgt_id),
316	mt_ram,
317	loader,
318	xram_latency);
319
320	std::ostringstream s_wt_xram;
321	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
322	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
323	dspin_ram_cmd_width,
324	dspin_ram_rsp_width>(
325	s_wt_xram.str().c_str(),
326	x_width + y_width + l_width);
327
328	///////////// RAM ROUTER(S)
329	std::ostringstream s_ram_router_cmd;
330	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
331	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
332	s_ram_router_cmd.str().c_str(),
333	x_id, y_id, // router coordinates in mesh
334	x_width, // x field width in first flit
335	y_width, // y field width in first flit
336	4, 4); // input & output fifo depths
337
338	std::ostringstream s_ram_router_rsp;
339	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
340	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
341	s_ram_router_rsp.str().c_str(),
342	x_id, y_id, // coordinates in mesh
343	x_width, // x field width in first flit
344	y_width, // y field width in first flit
345	4, 4); // input & output fifo depths
346
347
348	////////////////////// I/O CLUSTER ONLY ///////////////////////
349	if ( is_io )
350	{
351	/////////// IO_BRIDGE
352	std::ostringstream s_iob;
353	s_iob << "iob_" << x_id << "_" << y_id;
354	iob = new VciIoBridge<vci_param_int,
355	vci_param_ext>(
356	s_iob.str().c_str(),
357	mt_ram, // EXT network maptab
358	mt_int, // INT network maptab
359	mt_iox, // IOX network maptab
360	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
361	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
362	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
363	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
364	16, // cache line words
365	8, // IOTLB ways
366	8, // IOTLB sets
367	debug_start_cycle,
368	iob_debug_ok );
369
370	std::ostringstream s_iob_ram_wi;
371	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
372	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
373	dspin_ram_cmd_width,
374	dspin_ram_rsp_width>(
375	s_iob_ram_wi.str().c_str(),
376	vci_param_int::S);
377
378	std::ostringstream s_ram_xbar_cmd;
379	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
380	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
381	s_ram_xbar_cmd.str().c_str(), // name
382	mt_ram, // mapping table
383	x_id, y_id, // x, y
384	x_width, y_width, l_width, // x_width, y_width, l_width
385	2, 0, // local inputs, local outputs
386	2, 2, // in fifo, out fifo depths
387	true, // is cmd ?
388	false, // use routing table ?
389	false); // support broadcast ?
390
391	std::ostringstream s_ram_xbar_rsp;
392	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
393	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
394	s_ram_xbar_rsp.str().c_str(), // name
395	mt_ram, // mapping table
396	x_id, y_id, // x, y
397	x_width, y_width, l_width, // x_width, y_width, l_width
398	0, 2, // local inputs, local outputs
399	2, 2, // in fifo, out fifo depths
400	false, // is cmd ?
401	true, // use routing table ?
402	false); // support broadcast ?
403	} // end if IO
404
405	////////////////////////////////////
406	// Connections are defined here
407	////////////////////////////////////
408
409	// on coherence network : local srcid[proc] in [0...nb_procs-1]
410	// : local srcid[memc] = nb_procs
411
412	//////////////////////// internal CMD & RSP routers
413	int_router_cmd->p_clk (this->p_clk);
414	int_router_cmd->p_resetn (this->p_resetn);
415	int_router_rsp->p_clk (this->p_clk);
416	int_router_rsp->p_resetn (this->p_resetn);
417
418	for (int i = 0; i < 4; i++)
419	{
420	for(int k = 0; k < 3; k++)
421	{
422	int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]);
423	int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]);
424	}
425
426	for(int k = 0; k < 2; k++)
427	{
428	int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]);
429	int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]);
430	}
431	}
432
433	// local ports
434	int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d);
435	int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c);
436	int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c);
437	int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d);
438	int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c);
439	int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c);
440
441	int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d);
442	int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c);
443	int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d);
444	int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c);
445
446	///////////////////// CMD DSPIN local crossbar direct
447	int_xbar_d->p_clk (this->p_clk);
448	int_xbar_d->p_resetn (this->p_resetn);
449	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
450	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
451
452	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
453	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
454	int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma);
455	int_xbar_d->p_to_target[int_brom_tgt_id] (signal_int_vci_tgt_brom);
456	int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma);
457	for (size_t p = 0; p < nb_procs; p++)
458	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
459
460	if ( is_io )
461	{
462	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
463	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
464	}
465
466	int_wi_gate_d->p_clk (this->p_clk);
467	int_wi_gate_d->p_resetn (this->p_resetn);
468	int_wi_gate_d->p_vci (signal_int_vci_l2g);
469	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
470	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
471
472	int_wt_gate_d->p_clk (this->p_clk);
473	int_wt_gate_d->p_resetn (this->p_resetn);
474	int_wt_gate_d->p_vci (signal_int_vci_g2l);
475	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
476	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
477
478	////////////////////// M2P DSPIN local crossbar coherence
479	int_xbar_m2p_c->p_clk (this->p_clk);
480	int_xbar_m2p_c->p_resetn (this->p_resetn);
481	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
482	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
483	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
484	for (size_t p = 0; p < nb_procs; p++)
485	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
486
487	////////////////////////// P2M DSPIN local crossbar coherence
488	int_xbar_p2m_c->p_clk (this->p_clk);
489	int_xbar_p2m_c->p_resetn (this->p_resetn);
490	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
491	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
492	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
493	for (size_t p = 0; p < nb_procs; p++)
494	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
495
496	////////////////////// CLACK DSPIN local crossbar coherence
497	int_xbar_clack_c->p_clk (this->p_clk);
498	int_xbar_clack_c->p_resetn (this->p_resetn);
499	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
500	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
501	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
502	for (size_t p = 0; p < nb_procs; p++)
503	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
504
505	//////////////////////////////////// Processors
506	for (size_t p = 0; p < nb_procs; p++)
507	{
508	proc[p]->p_clk (this->p_clk);
509	proc[p]->p_resetn (this->p_resetn);
510	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
511	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
512	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
513	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
514
515	for ( size_t j = 0 ; j < 6 ; j++)
516	{
517	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
518	else proc[p]->p_irq[j] (signal_false);
519	}
520	}
521
522	///////////////////////////////////// XICU
523	xicu->p_clk (this->p_clk);
524	xicu->p_resetn (this->p_resetn);
525	xicu->p_vci (signal_int_vci_tgt_xicu);
526	for ( size_t i=0 ; i < 16 ; i++)
527	{
528	xicu->p_irq[i] (signal_proc_it[i]);
529	}
530	for ( size_t i=0 ; i < xcu_nb_inputs ; i++)
531	{
532	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
533	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
534	else xicu->p_hwi[i] (signal_false);
535	}
536
537	///////////////////////////////////// MEMC
538	memc->p_clk (this->p_clk);
539	memc->p_resetn (this->p_resetn);
540	memc->p_vci_ixr (signal_ram_vci_ini_memc);
541	memc->p_vci_tgt (signal_int_vci_tgt_memc);
542	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
543	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
544	memc->p_dspin_clack (signal_int_dspin_clack_memc);
545	memc->p_irq (signal_irq_memc);
546
547	// wrapper to RAM network
548	memc_ram_wi->p_clk (this->p_clk);
549	memc_ram_wi->p_resetn (this->p_resetn);
550	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
551	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
552	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
553
554	//////////////////////////////////// XRAM
555	xram->p_clk (this->p_clk);
556	xram->p_resetn (this->p_resetn);
557	xram->p_vci (signal_ram_vci_tgt_xram);
558
559	// wrapper to RAM network
560	xram_ram_wt->p_clk (this->p_clk);
561	xram_ram_wt->p_resetn (this->p_resetn);
562	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
563	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
564	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
565
566	/////////////////////////////////// MDMA
567	mdma->p_clk (this->p_clk);
568	mdma->p_resetn (this->p_resetn);
569	mdma->p_vci_target (signal_int_vci_tgt_mdma);
570	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
571	for (size_t i=0 ; i<nb_dmas ; i++)
572	mdma->p_irq[i] (signal_irq_mdma[i]);
573
574	/////////////////////////////////// BROM
575	brom->p_clk (this->p_clk);
576	brom->p_resetn (this->p_resetn);
577	brom->p_vci (signal_int_vci_tgt_brom);
578
579	//////////////////////////// RAM network CMD & RSP routers
580	ram_router_cmd->p_clk (this->p_clk);
581	ram_router_cmd->p_resetn (this->p_resetn);
582	ram_router_rsp->p_clk (this->p_clk);
583	ram_router_rsp->p_resetn (this->p_resetn);
584	for( size_t n=0 ; n<4 ; n++)
585	{
586	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
587	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
588	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
589	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
590	}
591
592	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
593	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
594
595	if ( is_io )
596	{
597	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
598	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
599	}
600	else
601	{
602	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
603	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
604	}
605
606	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
607	if ( is_io )
608	{
609	// IO bridge
610	iob->p_clk (this->p_clk);
611	iob->p_resetn (this->p_resetn);
612	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
613	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
614	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
615	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
616	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
617
618	// initiator wrapper to RAM network
619	iob_ram_wi->p_clk (this->p_clk);
620	iob_ram_wi->p_resetn (this->p_resetn);
621	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
622	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
623	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
624
625	// crossbar between MEMC and IOB to RAM network
626	ram_xbar_cmd->p_clk (this->p_clk);
627	ram_xbar_cmd->p_resetn (this->p_resetn);
628	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
629	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
630	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
631	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
632
633	ram_xbar_rsp->p_clk (this->p_clk);
634	ram_xbar_rsp->p_resetn (this->p_resetn);
635	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
636	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
637	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
638	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
639	}
640
641	SC_METHOD(init);
642
643	} // end constructor
644
645	tmpl(void)::init()
646	{
647	signal_ram_dspin_cmd_false.write = false;
648	signal_ram_dspin_rsp_false.read = true;
649	} // end init
650
651	}}
652
653
654	// Local Variables:
655	// tab-width: 4
656	// c-basic-offset: 4
657	// c-file-offsets:((innamespace . 0)(inline-open . 0))
658	// indent-tabs-mode: nil
659	// End:
660
661	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
662

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
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