source: branches/v4/softs/tsar_boot/include/mips32_registers.h @ 515

Last change on this file since 515 was 292, checked in by cfuguet, 11 years ago

Changing directory structure of the TSAR boot loader.
A README.txt file has been included to explain the new structure
and the MAKEFILE parameters.

Erasing the heap segment for the boot elf loader. All the work space
is allocated in the stack.

The stack size is defined in the include/defs.h.

Important modification in the reset.S file. The non-boot
processors (processor id != 0) wait in a low comsumption energy
mode to be wake up by processor 0 using an IPI. Each processor
has a private mailbox in the local XICU. The value written in
the mailbox will be used as address to jump by the processors.

The waking up of non-boot processors is not done in this boot loader
so it must be done in the application loaded.

The boot_loader_elf function loads into memory an executable .elf file
which must be placed in the BOOT_LOADER_LBA block of the disk. This
constant can be defined in the include/defs.h file.

File size: 1.6 KB
Line 
1/********************************************************************************/
2/*      File        : mips32_registers.h                                                                                        */
3/*      Author      : Alain Greiner                                                                                                     */
4/*      Date        : 26/03/2012                                                                                                        */
5/*  Modified by : Cesar Fuguet 10/02/2013                                                                               */
6/********************************************************************************/
7/*      We define mnemonics for MIPS32 registers                                                        */
8/********************************************************************************/
9
10#ifndef _MIPS32_REGISTERS_H
11#define _MIPS32_REGISTERS_H
12
13/* processor registers */
14
15#define zero            $0
16#define at              $at
17#define v0              $2
18#define v1              $3
19#define a0              $4
20#define a1              $5
21#define a2              $6
22#define a3              $7
23#define t0              $8
24#define t1              $9
25#define t2              $10
26#define t3              $11
27#define t4              $12
28#define t5              $13
29#define t6              $14
30#define t7              $15
31#define s0              $16
32#define s1              $17
33#define s2              $18
34#define s3              $19
35#define s4              $20
36#define s5              $21
37#define s6              $22
38#define s7              $23
39#define t8              $24
40#define t9              $25
41#define k0              $26
42#define k1              $27
43#define gp              $28
44#define sp              $29
45#define fp              $30
46#define ra              $31
47
48/* CP0 registers */
49
50#define CP0_COUNT       $9
51#define CP0_STATUS      $12,0
52#define CP0_CAUSE       $13,0
53#define CP0_EPC         $14,0
54#define CP0_EBASE       $15,1
55
56#endif
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